-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- Copyright (C) 2009, 2010 Dr. Juergen Sauermann
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-- Copyright (C) 2009, 2010 Dr. Juergen Sauermann
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--
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--
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-- This code is free software: you can redistribute it and/or modify
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-- This code is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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-- (at your option) any later version.
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--
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--
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-- This code is distributed in the hope that it will be useful,
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-- This code is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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-- GNU General Public License for more details.
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--
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--
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-- You should have received a copy of the GNU General Public License
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-- You should have received a copy of the GNU General Public License
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-- along with this code (see the file named COPYING).
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-- along with this code (see the file named COPYING).
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-- If not, see http://www.gnu.org/licenses/.
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-- If not, see http://www.gnu.org/licenses/.
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--
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- Module Name: opc_fetch - Behavioral
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-- Module Name: opc_fetch - Behavioral
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-- Create Date: 13:00:44 10/30/2009
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-- Create Date: 13:00:44 10/30/2009
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-- Description: the opcode fetch stage of a CPU.
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-- Description: the opcode fetch stage of a CPU.
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--
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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library IEEE;
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library IEEE;
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use IEEE.std_logic_1164.ALL;
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use IEEE.std_logic_1164.ALL;
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use IEEE.std_logic_ARITH.ALL;
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use IEEE.std_logic_ARITH.ALL;
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use IEEE.std_logic_UNSIGNED.ALL;
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use IEEE.std_logic_UNSIGNED.ALL;
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entity opc_fetch is
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entity opc_fetch is
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port ( I_CLK : in std_logic;
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port ( I_CLK : in std_logic;
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I_CLR : in std_logic;
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I_CLR : in std_logic;
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I_INTVEC : in std_logic_vector( 5 downto 0);
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I_INTVEC : in std_logic_vector( 5 downto 0);
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I_LOAD_PC : in std_logic;
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I_LOAD_PC : in std_logic;
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I_NEW_PC : in std_logic_vector(15 downto 0);
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I_NEW_PC : in std_logic_vector(15 downto 0);
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I_PM_ADR : in std_logic_vector(11 downto 0);
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I_PM_ADR : in std_logic_vector(11 downto 0);
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I_SKIP : in std_logic;
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I_SKIP : in std_logic;
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Q_OPC : out std_logic_vector(31 downto 0);
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Q_OPC : out std_logic_vector(31 downto 0);
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Q_PC : out std_logic_vector(15 downto 0);
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Q_PC : out std_logic_vector(15 downto 0);
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Q_PM_DOUT : out std_logic_vector( 7 downto 0);
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Q_PM_DOUT : out std_logic_vector( 7 downto 0);
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Q_T0 : out std_logic);
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Q_T0 : out std_logic);
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end opc_fetch;
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end opc_fetch;
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architecture Behavioral of opc_fetch is
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architecture Behavioral of opc_fetch is
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component prog_mem
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component prog_mem
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port ( I_CLK : in std_logic;
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port ( I_CLK : in std_logic;
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I_WAIT : in std_logic;
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I_WAIT : in std_logic;
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I_PC : in std_logic_vector (15 downto 0);
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I_PC : in std_logic_vector (15 downto 0);
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I_PM_ADR : in std_logic_vector (11 downto 0);
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I_PM_ADR : in std_logic_vector (11 downto 0);
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Q_OPC : out std_logic_vector (31 downto 0);
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Q_OPC : out std_logic_vector (31 downto 0);
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Q_PC : out std_logic_vector (15 downto 0);
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Q_PC : out std_logic_vector (15 downto 0);
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Q_PM_DOUT : out std_logic_vector ( 7 downto 0));
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Q_PM_DOUT : out std_logic_vector ( 7 downto 0));
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end component;
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end component;
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signal P_OPC : std_logic_vector(31 downto 0);
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signal P_OPC : std_logic_vector(31 downto 0);
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signal P_PC : std_logic_vector(15 downto 0);
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signal P_PC : std_logic_vector(15 downto 0);
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signal L_INVALIDATE : std_logic;
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signal L_INVALIDATE : std_logic;
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signal L_LONG_OP : std_logic;
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signal L_LONG_OP : std_logic;
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signal L_NEXT_PC : std_logic_vector(15 downto 0);
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signal L_NEXT_PC : std_logic_vector(15 downto 0);
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signal L_PC : std_logic_vector(15 downto 0);
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signal L_PC : std_logic_vector(15 downto 0);
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signal L_T0 : std_logic;
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signal L_T0 : std_logic;
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signal L_WAIT : std_logic;
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signal L_WAIT : std_logic;
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begin
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begin
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pmem : prog_mem
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pmem : prog_mem
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port map( I_CLK => I_CLK,
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port map( I_CLK => I_CLK,
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I_WAIT => L_WAIT,
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I_WAIT => L_WAIT,
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I_PC => L_NEXT_PC,
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I_PC => L_NEXT_PC,
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I_PM_ADR => I_PM_ADR,
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I_PM_ADR => I_PM_ADR,
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Q_OPC => P_OPC,
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Q_OPC => P_OPC,
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Q_PC => P_PC,
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Q_PC => P_PC,
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Q_PM_DOUT => Q_PM_DOUT);
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Q_PM_DOUT => Q_PM_DOUT);
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lpc: process(I_CLK)
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lpc: process(I_CLK)
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begin
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begin
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if (rising_edge(I_CLK)) then
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if (rising_edge(I_CLK)) then
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L_PC <= L_NEXT_PC;
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L_PC <= L_NEXT_PC;
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L_T0 <= not L_WAIT;
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L_T0 <= not L_WAIT;
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end if;
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end if;
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end process;
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end process;
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L_NEXT_PC <= X"0000" when (I_CLR = '1')
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L_NEXT_PC <= X"0000" when (I_CLR = '1')
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else L_PC when (L_WAIT = '1')
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else L_PC when (L_WAIT = '1')
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else I_NEW_PC when (I_LOAD_PC = '1')
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else I_NEW_PC when (I_LOAD_PC = '1')
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else L_PC + X"0002" when (L_LONG_OP = '1')
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else L_PC + X"0002" when (L_LONG_OP = '1')
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else L_PC + X"0001";
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else L_PC + X"0001";
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-- Two word opcodes:
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-- Two word opcodes:
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--
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--
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-- 9 3210
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-- 9 3210
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-- 1001 000d dddd 0000 kkkk kkkk kkkk kkkk - LDS
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-- 1001 000d dddd 0000 kkkk kkkk kkkk kkkk - LDS
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-- 1001 001d dddd 0000 kkkk kkkk kkkk kkkk - SDS
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-- 1001 001d dddd 0000 kkkk kkkk kkkk kkkk - SDS
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-- 1001 010k kkkk 110k kkkk kkkk kkkk kkkk - JMP
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-- 1001 010k kkkk 110k kkkk kkkk kkkk kkkk - JMP
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-- 1001 010k kkkk 111k kkkk kkkk kkkk kkkk - CALL
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-- 1001 010k kkkk 111k kkkk kkkk kkkk kkkk - CALL
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--
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--
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L_LONG_OP <= '1' when (((P_OPC(15 downto 9) = "1001010") and
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L_LONG_OP <= '1' when (((P_OPC(15 downto 9) = "1001010") and
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(P_OPC( 3 downto 2) = "11")) -- JMP, CALL
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(P_OPC( 3 downto 2) = "11")) -- JMP, CALL
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or ((P_OPC(15 downto 10) = "100100") and
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or ((P_OPC(15 downto 10) = "100100") and
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(P_OPC( 3 downto 0) = "0000"))) -- LDS, STS
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(P_OPC( 3 downto 0) = "0000"))) -- LDS, STS
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else '0';
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else '0';
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-- Two cycle opcodes:
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-- Two cycle opcodes:
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--
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--
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-- 10q0 qq0d dddd 1qqq - LDD (Y + q)
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-- 10q0 qq0d dddd 0qqq - LDD (Z + q)
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-- 1001 000d dddd .... - LDS etc.
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-- 1001 000d dddd .... - LDS etc.
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-- 1001 0101 0000 1000 - RET
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-- 1001 0101 0000 1000 - RET
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-- 1001 0101 0001 1000 - RETI
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-- 1001 0101 0001 1000 - RETI
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-- 1001 1001 AAAA Abbb - SBIC
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-- 1001 1001 AAAA Abbb - SBIC
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-- 1001 1011 AAAA Abbb - SBIS
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-- 1001 1011 AAAA Abbb - SBIS
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-- 1111 110r rrrr 0bbb - SBRC
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-- 1111 110r rrrr 0bbb - SBRC
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-- 1111 111r rrrr 0bbb - SBRS
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-- 1111 111r rrrr 0bbb - SBRS
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--
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--
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L_WAIT <= '0' when ((L_INVALIDATE = '1') or (I_INTVEC(5) = '1'))
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L_WAIT <= '0' when ((L_INVALIDATE = '1') or (I_INTVEC(5) = '1'))
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else L_T0 when ((P_OPC(15 downto 9) = "1001000" ) -- LDS etc.
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else L_T0 when ( ( (P_OPC(15 downto 14) = "10" ) -- LDD
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and (P_OPC(12) = '0')
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and (P_OPC( 9) = '0') )
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or ( P_OPC(15 downto 9) = "1001000") -- LDS etc.
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or ((P_OPC(15 downto 8) = "10010101") -- RET etc.
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or ((P_OPC(15 downto 8) = "10010101") -- RET etc.
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and (P_OPC(3 downto 0) /= "1010")) -- but not DEC
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and (P_OPC(3 downto 0) /= "1010")) -- but not DEC
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or ((P_OPC(15 downto 10) = "100110") -- SBIC, SBIS
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or ( ( P_OPC(15 downto 10) = "100110") -- SBI[CS]
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and (P_OPC(8) = '1'))
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and (P_OPC(8) = '1'))
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or (P_OPC(15 downto 10) = "111111")) -- SBRC, SBRS
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or (P_OPC(15 downto 10) = "111111")) -- SBR[CS]
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else '0';
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else '0';
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L_INVALIDATE <= I_CLR or I_SKIP;
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L_INVALIDATE <= I_CLR or I_SKIP;
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Q_OPC <= X"00000000" when (L_INVALIDATE = '1')
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Q_OPC <= X"00000000" when (L_INVALIDATE = '1')
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else P_OPC when (I_INTVEC(5) = '0')
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else P_OPC when (I_INTVEC(5) = '0')
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else (X"000000" & "00" & I_INTVEC); -- "interrupt opcode"
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else (X"000000" & "00" & I_INTVEC); -- "interrupt opcode"
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Q_PC <= P_PC;
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Q_PC <= P_PC;
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Q_T0 <= L_T0;
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Q_T0 <= L_T0;
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end Behavioral;
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end Behavioral;
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