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signal P_PC : std_logic_vector(15 downto 0);
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signal P_PC : std_logic_vector(15 downto 0);
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signal L_INVALIDATE : std_logic;
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signal L_INVALIDATE : std_logic;
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signal L_LONG_OP : std_logic;
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signal L_LONG_OP : std_logic;
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signal L_NEXT_PC : std_logic_vector(15 downto 0);
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signal L_NEXT_PC : std_logic_vector(15 downto 0);
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signal L_OPC_10q0_qq0 : std_logic;
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signal L_OPC_9_000 : std_logic;
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signal L_OPC_9_5_000x_8 : std_logic;
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signal L_OPC_9_5_110x_8 : std_logic;
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signal L_OPC_9_10x1 : std_logic;
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signal L_OPC_F_11 : std_logic;
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signal L_PC : std_logic_vector(15 downto 0);
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signal L_PC : std_logic_vector(15 downto 0);
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signal L_T0 : std_logic;
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signal L_T0 : std_logic;
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signal L_WAIT : std_logic;
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signal L_WAIT : std_logic;
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begin
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begin
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(P_OPC( 3 downto 0) = "0000"))) -- LDS, STS
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(P_OPC( 3 downto 0) = "0000"))) -- LDS, STS
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else '0';
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else '0';
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-- Two cycle opcodes:
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-- Two cycle opcodes:
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--
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--
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-- 10q0 qq0d dddd 1qqq - LDD (Y + q)
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-- 10q0 qq0d dddd 1qqq - LDD (Y + q) L_OPC_10q0_qq0
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-- 10q0 qq0d dddd 0qqq - LDD (Z + q)
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-- 10q0 qq0d dddd 0qqq - LDD (Z + q) L_OPC_10q0_qq0
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-- 1001 000d dddd .... - LDS etc.
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-- 1001 000d dddd .... - LDS etc. L_OPC_9_000
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-- 1001 0101 0000 1000 - RET
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-- 1001 0101 0000 1000 - RET L_OPC_9_5_000x_8
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-- 1001 0101 0001 1000 - RETI
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-- 1001 0101 0001 1000 - RETI L_OPC_9_5_000x_8
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-- 1001 1001 AAAA Abbb - SBIC
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-- 1001 0101 1100 1000 - LPM L_OPC_9_5_110x_8
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-- 1001 1011 AAAA Abbb - SBIS
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-- 1001 0101 1101 1000 - ELPM L_OPC_9_5_110x_8
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-- 1111 110r rrrr 0bbb - SBRC
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-- 1001 1001 AAAA Abbb - SBIC L_OPC_9_10x1
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-- 1111 111r rrrr 0bbb - SBRS
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-- 1001 1011 AAAA Abbb - SBIS L_OPC_9_10x1
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-- 1111 110r rrrr 0bbb - SBRC L_OPC_F_11
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-- 1111 111r rrrr 0bbb - SBRS L_OPC_F_11
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--
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--
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L_WAIT <= '0' when ((L_INVALIDATE = '1') or (I_INTVEC(5) = '1'))
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L_OPC_10q0_qq0 <= '1' when ((P_OPC(15 downto 14) = "10" )
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else L_T0 when ( ( (P_OPC(15 downto 14) = "10" ) -- LDD
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and (P_OPC(12) = '0')
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and (P_OPC(12) = '0')
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and (P_OPC( 9) = '0') )
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and (P_OPC( 9) = '0')) else '0';
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or ( P_OPC(15 downto 9) = "1001000") -- LDS etc.
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L_OPC_9_000 <= '1' when ( P_OPC(15 downto 9) = "1001000") else '0';
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or ( ( P_OPC(15 downto 8) = "10010101") -- RET etc.
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L_OPC_9_5_000x_8 <= '1' when ((P_OPC(15 downto 5) = "10010101000")
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and (P_OPC( 3 downto 0) /= "1010")) -- but not DEC
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and (P_OPC( 3 downto 0) = "1000")) else '0';
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or ( ( P_OPC(15 downto 10) = "100110") -- SBI[CS]
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L_OPC_9_5_110x_8 <= '1' when ((P_OPC(15 downto 5) = "10010101110")
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and (P_OPC(8) = '1'))
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and (P_OPC( 3 downto 0) = "1000")) else '0';
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or (P_OPC(15 downto 10) = "111111")) -- SBR[CS]
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L_OPC_9_10x1 <= '1' when ((P_OPC(15 downto 10) = "100110")
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else '0';
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and (P_OPC(8) = '1')) else '0';
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L_OPC_F_11 <= '1' when ( P_OPC(15 downto 10) = "111111") else '0';
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L_WAIT <= L_T0 and (L_OPC_10q0_qq0 or -- LDD
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L_OPC_9_000 or -- LDS, LD, LPM, POP
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L_OPC_9_5_000x_8 or -- RET, RETI, LPM
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L_OPC_9_5_110x_8 or -- LPM, ELPM
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L_OPC_9_10x1 or -- SBIC, SBIS
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L_OPC_F_11) -- SBRC, SBRS
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and (not L_INVALIDATE)
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and (not I_INTVEC(5));
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L_INVALIDATE <= I_CLR or I_SKIP;
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L_INVALIDATE <= I_CLR or I_SKIP;
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Q_OPC <= X"00000000" when (L_INVALIDATE = '1')
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Q_OPC <= X"00000000" when (L_INVALIDATE = '1')
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else P_OPC when (I_INTVEC(5) = '0')
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else P_OPC when (I_INTVEC(5) = '0')
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