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[/] [cpu_lecture/] [trunk/] [src/] [uart.vhd] - Diff between revs 2 and 25

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Rev 2 Rev 25
Line 81... Line 81...
            I_CLR       : in  std_logic;
            I_CLR       : in  std_logic;
            I_CE_1      : in  std_logic;
            I_CE_1      : in  std_logic;
            I_DATA      : in  std_logic_vector(7 downto 0);
            I_DATA      : in  std_logic_vector(7 downto 0);
            I_FLAG      : in  std_logic;
            I_FLAG      : in  std_logic;
 
 
            Q_TX        : out std_logic;
            Q_TX_N      : out std_logic;
            Q_FLAG      : out std_logic);
            Q_BUSY      : out std_logic);
end component;
end component;
 
 
signal L_RX_OLD_FLAG    : std_logic;
signal L_RX_OLD_FLAG    : std_logic;
 
signal L_RX_READY       : std_logic;
signal L_TX_FLAG        : std_logic;
signal L_TX_FLAG        : std_logic;
signal L_TX_FLAGQ       : std_logic;
 
signal L_TX_DATA        : std_logic_vector(7 downto 0);
signal L_TX_DATA        : std_logic_vector(7 downto 0);
signal L_RX_READY       : std_logic;
 
 
 
begin
begin
 
 
    Q_RX_READY <= L_RX_READY;
    Q_RX_READY <= L_RX_READY;
    Q_TX_BUSY  <= L_TX_FLAG xor L_TX_FLAGQ;
 
 
 
    baud: baudgen
    baud: baudgen
    generic map(CLOCK_FREQ  => CLOCK_FREQ,
    generic map(CLOCK_FREQ  => CLOCK_FREQ,
                BAUD_RATE   => BAUD_RATE)
                BAUD_RATE   => BAUD_RATE)
    port map(   I_CLK       => I_CLK,
    port map(   I_CLK       => I_CLK,
Line 121... Line 119...
                I_CLR   => I_CLR,
                I_CLR   => I_CLR,
                I_CE_1  => B_CE_1,
                I_CE_1  => B_CE_1,
                I_DATA  => L_TX_DATA,
                I_DATA  => L_TX_DATA,
                I_FLAG  => L_TX_FLAG,
                I_FLAG  => L_TX_FLAG,
 
 
                Q_TX    => Q_TX,
                Q_TX_N  => Q_TX,
                Q_FLAG  => L_TX_FLAGQ);
                Q_BUSY  => Q_TX_BUSY);
 
 
    process(I_CLK)
    process(I_CLK)
    begin
    begin
        if (rising_edge(I_CLK)) then
        if (rising_edge(I_CLK)) then
            if (I_CLR = '1') then
            if (I_CLR = '1') then
 
                L_RX_OLD_FLAG <= R_RX_FLAG;
 
                L_RX_READY <= '0';
                L_TX_FLAG <= '0';
                L_TX_FLAG <= '0';
                L_TX_DATA <= X"33";
                L_TX_DATA <= X"33";
            else
            else
                if (I_RD = '1') then          -- read Rx data
                if (I_RD = '1') then          -- read Rx data
                    L_RX_READY    <= '0';
                    L_RX_READY    <= '0';
Line 140... Line 140...
                if (I_WE = '1') then          -- write Tx data
                if (I_WE = '1') then          -- write Tx data
                    L_TX_FLAG  <= not L_TX_FLAG;
                    L_TX_FLAG  <= not L_TX_FLAG;
                    L_TX_DATA <= I_TX_DATA;
                    L_TX_DATA <= I_TX_DATA;
                end if;
                end if;
 
 
                if (R_RX_FLAG /= L_RX_OLD_FLAG) then
                if (L_RX_OLD_FLAG /= R_RX_FLAG) then
 
                    L_RX_OLD_FLAG <= R_RX_FLAG;
                    L_RX_READY <= '1';
                    L_RX_READY <= '1';
                end if;
                end if;
 
 
                L_RX_OLD_FLAG <= R_RX_FLAG;
 
            end if;
            end if;
        end if;
        end if;
    end process;
    end process;
 
 
end Behavioral;
end Behavioral;

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