URL https://opencores.org/ocsvn/ddr3_synthesizable_bfm/ddr3_synthesizable_bfm/trunk

Subversion Repositories ddr3_synthesizable_bfm

[/] [ddr3_synthesizable_bfm/] [trunk/] [rtl/] [ddr3_simple4.v] - Diff between revs 2 and 3

Rev 2	Rev 3
Line 16...	Line 16...
`* License along with this library; if not, write to the Free Software`	`* License along with this library; if not, write to the Free Software`
`* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307`	`* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307`
`* USA`	`* USA`
`*`	`*`
`*`	`*`
`* simple implementation of DDR3 Memory`	`* Simple implementation of DDR3 Memory`
`* will only reponse to write and read request`	`* will only reponse to write and read request`
`* parameter`	`* parameter`
`* count start from t0,t2,t2...`	`* count start from t0,t2,t2...`
`* ck _\|-\|_\|-\|_\|-\|_\|-\|_`	`* ck _\|-\|_\|-\|_\|-\|_\|-\|_`
`*`	`*`
`* cs#---\|___\|---------`	`* cs#---\|___\|---------`
`*`	`*`
`* \| \| \|`	`* \| \| \|`
`* t0 t1 t2 ....`	`* t0 t1 t2 ....`
`*`	`*`
`*2/12/2011: not able to handle multiple bank opening`
`*2/12/2011: not using DM signals`
`*`
`*/`	`*/`

`timescale 1ps / 1ps	`timescale 1ps / 1ps

`module ddr3_simple4#(`	`module ddr3_simple4#(`