/*
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/*
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*DDR3 Simple Synthesizable Memory BFM
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*DDR3 Simple Synthesizable Memory BFM
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*2010-2011 sclai <laikos@yahoo.com>
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*2010-2011 sclai <laikos@yahoo.com>
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*
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*
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*This library is free software; you can redistribute it and/or modify it
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*This library is free software; you can redistribute it and/or modify it
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* under the terms of the GNU Lesser General Public License as published by
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* under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation; either version 2.1 of the License,
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* the Free Software Foundation; either version 2.1 of the License,
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* or (at your option) any later version.
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* or (at your option) any later version.
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*
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*
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* This library is distributed in the hope that it will be useful, but
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* This library is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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* Lesser General Public License for more details.
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*
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*
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* You should have received a copy of the GNU Lesser General Public
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
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* USA
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* USA
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*
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*
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*
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*
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* simple implementation of DDR3 Memory
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* Simple implementation of DDR3 Memory
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* will only reponse to write and read request
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* will only reponse to write and read request
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* parameter
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* parameter
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* count start from t0,t2,t2...
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* count start from t0,t2,t2...
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* ck _|-|_|-|_|-|_|-|_
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* ck _|-|_|-|_|-|_|-|_
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*
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*
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* cs#---|___|---------
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* cs#---|___|---------
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*
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*
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* | | |
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* | | |
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* t0 t1 t2 ....
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* t0 t1 t2 ....
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*
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*
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*2/12/2011: not able to handle multiple bank opening
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*2/12/2011: not using DM signals
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*
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*/
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*/
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`timescale 1ps / 1ps
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`timescale 1ps / 1ps
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module ddr3_simple4#(
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module ddr3_simple4#(
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parameter MEM_DQ_WIDTH =8,
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parameter MEM_DQ_WIDTH =8,
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parameter MEM_BA_WIDTH =3,
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parameter MEM_BA_WIDTH =3,
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parameter MEM_ROW_WIDTH =13,
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parameter MEM_ROW_WIDTH =13,
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parameter MEM_COL_WIDTH =13,
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parameter MEM_COL_WIDTH =13,
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parameter MEM_TRTP =6,
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parameter MEM_TRTP =6,
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parameter MEM_TRCD =11,
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parameter MEM_TRCD =11,
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parameter MEM_TWL =8,
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parameter MEM_TWL =8,
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parameter MEM_TRL =6,
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parameter MEM_TRL =6,
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parameter MEM_ACT_CMD =7 //activates to command
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parameter MEM_ACT_CMD =7 //activates to command
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)(
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)(
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input wire [MEM_ROW_WIDTH-1:0] a,
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input wire [MEM_ROW_WIDTH-1:0] a,
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input wire [ MEM_BA_WIDTH-1:0] ba,
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input wire [ MEM_BA_WIDTH-1:0] ba,
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input wire ck,
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input wire ck,
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input wire ck_n,
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input wire ck_n,
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input wire cke,
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input wire cke,
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input wire cs_n,
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input wire cs_n,
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input wire dm,
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input wire dm,
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input wire ras_n,
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input wire ras_n,
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input wire cas_n,
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input wire cas_n,
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input wire we_n,
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input wire we_n,
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input wire reset_n,
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input wire reset_n,
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inout wire [MEM_DQ_WIDTH-1:0] dq,
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inout wire [MEM_DQ_WIDTH-1:0] dq,
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inout wire dqs,
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inout wire dqs,
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inout wire dqs_n,
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inout wire dqs_n,
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input wire odt
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input wire odt
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);
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);
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//definitions
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//definitions
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localparam OPCODE_PRECHARGE = 4'b0010;
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localparam OPCODE_PRECHARGE = 4'b0010;
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localparam OPCODE_ACTIVATE = 4'b0011;
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localparam OPCODE_ACTIVATE = 4'b0011;
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localparam OPCODE_WRITE = 4'b0100;
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localparam OPCODE_WRITE = 4'b0100;
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localparam OPCODE_READ = 4'b0101;
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localparam OPCODE_READ = 4'b0101;
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localparam OPCODE_MRS = 4'b0000;
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localparam OPCODE_MRS = 4'b0000;
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localparam OPCODE_REFRESH = 4'b0001;
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localparam OPCODE_REFRESH = 4'b0001;
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localparam OPCODE_DES = 4'b1000;
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localparam OPCODE_DES = 4'b1000;
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localparam OPCODE_ZQC = 4'b0110;
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localparam OPCODE_ZQC = 4'b0110;
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localparam OPCODE_NOP = 4'b0111;
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localparam OPCODE_NOP = 4'b0111;
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localparam BL8 = 1'b1;
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localparam BL8 = 1'b1;
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localparam BC4 = 1'b0;
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localparam BC4 = 1'b0;
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//mode registers
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//mode registers
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reg [31:0] mr0;
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reg [31:0] mr0;
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reg [31:0] mr2;
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reg [31:0] mr2;
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reg [31:0] mr3;
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reg [31:0] mr3;
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wire [35:0] write_add;
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wire [35:0] write_add;
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wire [35:0] read_add;
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wire [35:0] read_add;
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wire [3:0] write_cmd;
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wire [3:0] write_cmd;
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wire [3:0] read_cmd;
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wire [3:0] read_cmd;
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(* keep *)wire [(MEM_DQ_WIDTH*2)-1:0] read_data;
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(* keep *)wire [(MEM_DQ_WIDTH*2)-1:0] read_data;
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reg [ 2:0] last_bank;
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reg [ 2:0] last_bank;
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reg [15:0] last_row;
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reg [15:0] last_row;
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reg [3:0] last_write_cmd;
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reg [3:0] last_write_cmd;
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reg [3:0] last_read_cmd;
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reg [3:0] last_read_cmd;
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reg [35:0] last_write_add;
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reg [35:0] last_write_add;
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reg [35:0] last_read_add;
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reg [35:0] last_read_add;
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reg write_address12;
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reg write_address12;
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reg read_address12;
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reg read_address12;
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//bank tracker
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//bank tracker
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reg [MEM_ROW_WIDTH-1:0]opened_row[(2**MEM_BA_WIDTH)-1:0];
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reg [MEM_ROW_WIDTH-1:0]opened_row[(2**MEM_BA_WIDTH)-1:0];
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//row tracker
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//row tracker
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wire [MEM_DQ_WIDTH-1:0] dq_out;
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wire [MEM_DQ_WIDTH-1:0] dq_out;
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reg [MEM_DQ_WIDTH-1:0] dq_in0;
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reg [MEM_DQ_WIDTH-1:0] dq_in0;
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(* keep *) wire [MEM_DQ_WIDTH-1:0] data_hi;
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(* keep *) wire [MEM_DQ_WIDTH-1:0] data_hi;
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(* keep *) wire [MEM_DQ_WIDTH-1:0] data_lo;
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(* keep *) wire [MEM_DQ_WIDTH-1:0] data_lo;
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(* keep *) wire data_hi_dm;
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(* keep *) wire data_hi_dm;
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(* keep *) wire data_lo_dm;
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(* keep *) wire data_lo_dm;
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//IDDR
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//IDDR
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my_iddrx8 iddrx8_inst(
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my_iddrx8 iddrx8_inst(
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.clk(ck),
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.clk(ck),
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.io(dq),
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.io(dq),
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.d0(data_lo),
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.d0(data_lo),
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.d1(data_hi)
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.d1(data_hi)
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);
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);
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my_iddrx8 iddrx8_dm_inst(
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my_iddrx8 iddrx8_dm_inst(
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.clk(ck),
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.clk(ck),
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.io(dm),
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.io(dm),
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.d0(data_lo_dm),
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.d0(data_lo_dm),
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.d1(data_hi_dm)
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.d1(data_hi_dm)
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);
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);
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//ODDR
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//ODDR
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my_oddrx8 oddrx8_inst(
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my_oddrx8 oddrx8_inst(
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.clk(ck),
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.clk(ck),
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.d0(read_data[ MEM_DQ_WIDTH-1:0 ]),
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.d0(read_data[ MEM_DQ_WIDTH-1:0 ]),
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.d1(read_data[(MEM_DQ_WIDTH*2)-1:MEM_DQ_WIDTH]),
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.d1(read_data[(MEM_DQ_WIDTH*2)-1:MEM_DQ_WIDTH]),
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.io(dq_out)
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.io(dq_out)
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);
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);
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//double data rate
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//double data rate
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always @(posedge ck )
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always @(posedge ck )
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begin
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begin
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if(reset_n==1'b0)
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if(reset_n==1'b0)
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begin
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begin
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last_bank <=4'h0;
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last_bank <=4'h0;
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last_row <=16'h0000;
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last_row <=16'h0000;
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end
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end
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else
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else
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begin
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begin
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case({cs_n,ras_n,cas_n,we_n})
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case({cs_n,ras_n,cas_n,we_n})
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/*
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/*
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OPCODE_PRECHARGE :begin
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OPCODE_PRECHARGE :begin
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$display("t=%d,PRECHARGE",vip_clk);
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$display("t=%d,PRECHARGE",vip_clk);
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end
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end
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*/
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*/
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OPCODE_ACTIVATE :begin
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OPCODE_ACTIVATE :begin
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opened_row [ba] <={{(16-MEM_ROW_WIDTH){1'b0}},a[MEM_ROW_WIDTH-1:0]};
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opened_row [ba] <={{(16-MEM_ROW_WIDTH){1'b0}},a[MEM_ROW_WIDTH-1:0]};
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end
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end
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/*
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/*
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OPCODE_DES :begin
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OPCODE_DES :begin
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$display("t=%d,DES",vip_clk);
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$display("t=%d,DES",vip_clk);
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end
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end
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OPCODE_MRS :begin
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OPCODE_MRS :begin
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$display("t=%d,MRS",vip_clk);
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$display("t=%d,MRS",vip_clk);
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end
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end
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OPCODE_NOP :begin
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OPCODE_NOP :begin
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//$display("t=%d,NOP",vip_clk);
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//$display("t=%d,NOP",vip_clk);
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end
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end
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*/
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*/
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OPCODE_READ :begin
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OPCODE_READ :begin
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last_read_add <={ba,opened_row[ba],{{(16-MEM_COL_WIDTH){1'b0}},a[MEM_COL_WIDTH-1:0]}};
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last_read_add <={ba,opened_row[ba],{{(16-MEM_COL_WIDTH){1'b0}},a[MEM_COL_WIDTH-1:0]}};
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last_read_cmd <=OPCODE_READ;
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last_read_cmd <=OPCODE_READ;
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end
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end
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OPCODE_WRITE :begin
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OPCODE_WRITE :begin
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last_write_add <={ba,opened_row[ba],{{(16-MEM_COL_WIDTH){1'b0}},a[MEM_COL_WIDTH-1:0]}};
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last_write_add <={ba,opened_row[ba],{{(16-MEM_COL_WIDTH){1'b0}},a[MEM_COL_WIDTH-1:0]}};
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last_write_cmd <=OPCODE_WRITE;
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last_write_cmd <=OPCODE_WRITE;
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end
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end
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/*
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/*
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OPCODE_ZQC :begin
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OPCODE_ZQC :begin
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$display("t=%d,ZQC",vip_clk);
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$display("t=%d,ZQC",vip_clk);
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end*/
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end*/
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default:begin
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default:begin
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last_read_cmd <=OPCODE_NOP;
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last_read_cmd <=OPCODE_NOP;
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last_write_cmd <=OPCODE_NOP;
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last_write_cmd <=OPCODE_NOP;
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end
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end
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endcase
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endcase
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end // end reset
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end // end reset
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end // end always@(*)
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end // end always@(*)
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//cmd
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//cmd
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//read
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//read
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ddr3_sr4 #(
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ddr3_sr4 #(
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.PIPE_LEN(MEM_TRL)
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.PIPE_LEN(MEM_TRL)
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)ddr3_read_cmd_sr(
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)ddr3_read_cmd_sr(
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.clk(ck),
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.clk(ck),
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.shift_in(last_read_cmd),
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.shift_in(last_read_cmd),
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.shift_out(read_cmd)
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.shift_out(read_cmd)
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);
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);
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//bank, row, col
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//bank, row, col
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ddr3_sr36 #(
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ddr3_sr36 #(
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.PIPE_LEN(MEM_TRL+1)
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.PIPE_LEN(MEM_TRL+1)
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)ddr3_read_add_sr(
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)ddr3_read_add_sr(
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.clk(ck),
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.clk(ck),
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.shift_in(last_read_add),
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.shift_in(last_read_add),
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.shift_out(read_add)
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.shift_out(read_add)
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);
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);
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//cmd
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//cmd
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//write
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//write
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ddr3_sr4#(
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ddr3_sr4#(
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.PIPE_LEN(MEM_TWL)
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.PIPE_LEN(MEM_TWL)
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)ddr3_write_cmd_sr(
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)ddr3_write_cmd_sr(
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.clk(ck),
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.clk(ck),
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.shift_in(last_write_cmd),
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.shift_in(last_write_cmd),
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.shift_out(write_cmd)
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.shift_out(write_cmd)
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);
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);
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//bank, row, col
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//bank, row, col
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ddr3_sr36#(
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ddr3_sr36#(
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.PIPE_LEN(MEM_TWL+1) //have to be a cycle late to wait for IDDR latency
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.PIPE_LEN(MEM_TWL+1) //have to be a cycle late to wait for IDDR latency
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) ddr3_write_add_sr(
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) ddr3_write_add_sr(
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.clk(ck),
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.clk(ck),
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.shift_in(last_write_add),
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.shift_in(last_write_add),
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.shift_out(write_add)
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.shift_out(write_add)
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);
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);
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//write fsm
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//write fsm
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localparam WR_D0 =4'd0;
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localparam WR_D0 =4'd0;
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localparam WR_D1 =4'd1;
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localparam WR_D1 =4'd1;
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localparam WR_D2 =4'd2;
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localparam WR_D2 =4'd2;
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localparam WR_D3 =4'd3;
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localparam WR_D3 =4'd3;
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localparam WR_IDLE=4'd5;
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localparam WR_IDLE=4'd5;
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reg [3:0] write_state;
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reg [3:0] write_state;
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reg mem_we;
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reg mem_we;
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reg [2:0] write_col;
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reg [2:0] write_col;
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always@(posedge ck)
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always@(posedge ck)
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begin
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begin
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if(reset_n==1'b0)
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if(reset_n==1'b0)
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begin
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begin
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write_state<=WR_IDLE;
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write_state<=WR_IDLE;
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mem_we<=1'b0;
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mem_we<=1'b0;
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write_col<=0;
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write_col<=0;
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end
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end
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else
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else
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begin
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begin
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case(write_state)
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case(write_state)
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WR_IDLE:begin
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WR_IDLE:begin
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write_col<=0;
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write_col<=0;
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if(write_cmd==OPCODE_WRITE)
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if(write_cmd==OPCODE_WRITE)
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begin
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begin
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write_state<=WR_D0;
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write_state<=WR_D0;
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mem_we<=1'b1;
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mem_we<=1'b1;
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end
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end
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else
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else
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begin
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begin
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write_state<=WR_IDLE;
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write_state<=WR_IDLE;
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mem_we<=1'b0;
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mem_we<=1'b0;
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end
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end
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end
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end
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WR_D0:begin
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WR_D0:begin
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write_address12<=write_add[12];
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write_address12<=write_add[12];
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write_state<=WR_D1;
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write_state<=WR_D1;
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write_col<=write_col+1'b1;
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write_col<=write_col+1'b1;
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$display("%m: at time %t\tWRITE BANK[%x]\tROW[%x]\tCOL[%x]\tWR D0: %x-%x",$time,write_add[34:32],write_add[31:16],write_add[15:0],data_hi,data_lo);
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$display("%m: at time %t\tWRITE BANK[%x]\tROW[%x]\tCOL[%x]\tWR D0: %x-%x",$time,write_add[34:32],write_add[31:16],write_add[15:0],data_hi,data_lo);
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end
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end
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WR_D1:begin
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WR_D1:begin
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if(write_address12==1'b1)
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if(write_address12==1'b1)
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begin
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begin
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write_state<=WR_D2;
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write_state<=WR_D2;
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write_col<=write_col+1'b1;
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write_col<=write_col+1'b1;
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end
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end
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else if (write_cmd==OPCODE_WRITE)
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else if (write_cmd==OPCODE_WRITE)
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begin
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begin
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write_state<=WR_D0;
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write_state<=WR_D0;
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write_col<=0;
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write_col<=0;
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end
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end
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else
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else
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begin
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begin
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write_state<=WR_IDLE;
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write_state<=WR_IDLE;
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mem_we<=1'b0;
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mem_we<=1'b0;
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end
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end
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$display("%m: at time %t\tWRITE BANK[%x]\tROW[%x]\tCOL[%x]\tWR D1: %x-%x",$time,write_add[34:32],write_add[31:16],write_add[15:0],data_hi,data_lo);
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$display("%m: at time %t\tWRITE BANK[%x]\tROW[%x]\tCOL[%x]\tWR D1: %x-%x",$time,write_add[34:32],write_add[31:16],write_add[15:0],data_hi,data_lo);
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end
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end
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WR_D2:begin
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WR_D2:begin
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write_state<=WR_D3;
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write_state<=WR_D3;
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write_col<=write_col+1'b1;
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write_col<=write_col+1'b1;
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$display("%m: at time %t\tWRITE BANK[%x]\tROW[%x]\tCOL[%x]\tWR D2: %x-%x",$time,write_add[34:32],write_add[31:16],write_add[15:0],data_hi,data_lo);
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$display("%m: at time %t\tWRITE BANK[%x]\tROW[%x]\tCOL[%x]\tWR D2: %x-%x",$time,write_add[34:32],write_add[31:16],write_add[15:0],data_hi,data_lo);
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end
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end
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WR_D3:begin
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WR_D3:begin
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$display("%m: at time %t\tWRITE BANK[%x]\tROW[%x]\tCOL[%x]\tWR D3: %x-%x",$time,write_add[34:32],write_add[31:16],write_add[15:0],data_hi,data_lo);
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$display("%m: at time %t\tWRITE BANK[%x]\tROW[%x]\tCOL[%x]\tWR D3: %x-%x",$time,write_add[34:32],write_add[31:16],write_add[15:0],data_hi,data_lo);
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|
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//write_col<=write_col+1'b1;
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//write_col<=write_col+1'b1;
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if (write_cmd==OPCODE_WRITE)
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if (write_cmd==OPCODE_WRITE)
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begin
|
begin
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write_state<=WR_D0;
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write_state<=WR_D0;
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write_col<=0;
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write_col<=0;
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end
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end
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else
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else
|
begin
|
begin
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write_state<=WR_IDLE;
|
write_state<=WR_IDLE;
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mem_we<=1'b0;
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mem_we<=1'b0;
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end
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end
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end
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end
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endcase
|
endcase
|
end //endif
|
end //endif
|
end
|
end
|
|
|
|
|
//read fsm
|
//read fsm
|
localparam RD_D0 =4'd0;
|
localparam RD_D0 =4'd0;
|
localparam RD_D1 =4'd1;
|
localparam RD_D1 =4'd1;
|
localparam RD_D2 =4'd2;
|
localparam RD_D2 =4'd2;
|
localparam RD_D3 =4'd3;
|
localparam RD_D3 =4'd3;
|
localparam RD_IDLE=4'd5;
|
localparam RD_IDLE=4'd5;
|
|
|
reg [3:0] read_state;
|
reg [3:0] read_state;
|
reg [2:0] read_col;
|
reg [2:0] read_col;
|
reg send_dq;
|
reg send_dq;
|
reg send_dqs0;
|
reg send_dqs0;
|
reg send_dqs1;
|
reg send_dqs1;
|
|
|
always@(posedge ck)
|
always@(posedge ck)
|
begin
|
begin
|
if(reset_n==1'b0)
|
if(reset_n==1'b0)
|
begin
|
begin
|
read_state<=RD_IDLE;
|
read_state<=RD_IDLE;
|
read_col <=0;
|
read_col <=0;
|
send_dq <=0;
|
send_dq <=0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
case(read_state)
|
case(read_state)
|
RD_IDLE:begin
|
RD_IDLE:begin
|
read_col<=0;
|
read_col<=0;
|
send_dq<=0;
|
send_dq<=0;
|
if(read_cmd==OPCODE_READ)
|
if(read_cmd==OPCODE_READ)
|
begin
|
begin
|
read_state<=RD_D0;
|
read_state<=RD_D0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
read_state<=RD_IDLE;
|
read_state<=RD_IDLE;
|
end
|
end
|
end
|
end
|
RD_D0:begin
|
RD_D0:begin
|
read_address12<=read_add[12];
|
read_address12<=read_add[12];
|
read_state<=RD_D1;
|
read_state<=RD_D1;
|
read_col<=read_col+1'b1;
|
read_col<=read_col+1'b1;
|
send_dq <=1'b1;
|
send_dq <=1'b1;
|
$display("%m: at time %t\tREAD BANK[%x]\tROW[%x]\tCOL[%x]\tRD D0",$time,read_add[34:32],read_add[31:16],read_add[15:0]);
|
$display("%m: at time %t\tREAD BANK[%x]\tROW[%x]\tCOL[%x]\tRD D0",$time,read_add[34:32],read_add[31:16],read_add[15:0]);
|
end
|
end
|
RD_D1:begin
|
RD_D1:begin
|
if(read_address12==1'b1)
|
if(read_address12==1'b1)
|
begin
|
begin
|
read_state<=RD_D2;
|
read_state<=RD_D2;
|
read_col<=read_col+1'b1;
|
read_col<=read_col+1'b1;
|
end
|
end
|
else if (read_cmd==OPCODE_READ)
|
else if (read_cmd==OPCODE_READ)
|
begin
|
begin
|
read_state<=RD_D0;
|
read_state<=RD_D0;
|
read_col<=0;
|
read_col<=0;
|
send_dq <=1'b1;
|
send_dq <=1'b1;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
read_state<=RD_IDLE;
|
read_state<=RD_IDLE;
|
//send_dq <=1'b0;
|
//send_dq <=1'b0;
|
end
|
end
|
$display("%m: at time %t\tREAD BANK[%x]\tROW[%x]\tCOL[%x]\tRD D1",$time,read_add[34:32],read_add[31:16],read_add[15:0]);
|
$display("%m: at time %t\tREAD BANK[%x]\tROW[%x]\tCOL[%x]\tRD D1",$time,read_add[34:32],read_add[31:16],read_add[15:0]);
|
end
|
end
|
RD_D2:begin
|
RD_D2:begin
|
read_state<=RD_D3;
|
read_state<=RD_D3;
|
read_col<=read_col+1'b1;
|
read_col<=read_col+1'b1;
|
send_dq <=1'b1;
|
send_dq <=1'b1;
|
$display("%m: at time %t\tREAD BANK[%x]\tROW[%x]\tCOL[%x]\tRD D2",$time,read_add[34:32],read_add[31:16],read_add[15:0]);
|
$display("%m: at time %t\tREAD BANK[%x]\tROW[%x]\tCOL[%x]\tRD D2",$time,read_add[34:32],read_add[31:16],read_add[15:0]);
|
end
|
end
|
RD_D3:begin
|
RD_D3:begin
|
//write_col<=write_col+1'b1;
|
//write_col<=write_col+1'b1;
|
if (read_cmd==OPCODE_READ)
|
if (read_cmd==OPCODE_READ)
|
begin
|
begin
|
read_state<=RD_D0;
|
read_state<=RD_D0;
|
read_col<=0;
|
read_col<=0;
|
send_dq <=1'b1;
|
send_dq <=1'b1;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
read_state<=RD_IDLE;
|
read_state<=RD_IDLE;
|
read_col<=0;
|
read_col<=0;
|
//send_dq <=1'b0;
|
//send_dq <=1'b0;
|
end
|
end
|
$display("%m: at time %t\tREAD BANK[%x]\tROW[%x]\tCOL[%x]\tRD D3",$time,read_add[34:32],read_add[31:16],read_add[15:0]);
|
$display("%m: at time %t\tREAD BANK[%x]\tROW[%x]\tCOL[%x]\tRD D3",$time,read_add[34:32],read_add[31:16],read_add[15:0]);
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
|
|
end //end always
|
end //end always
|
|
|
//dqs fsm
|
//dqs fsm
|
always @(posedge ck_n)
|
always @(posedge ck_n)
|
begin
|
begin
|
if(reset_n==1'b0)
|
if(reset_n==1'b0)
|
begin
|
begin
|
send_dqs1<=0;
|
send_dqs1<=0;
|
send_dqs0<=0;
|
send_dqs0<=0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
if(read_cmd==OPCODE_READ)
|
if(read_cmd==OPCODE_READ)
|
begin
|
begin
|
send_dqs1<=1'b1;
|
send_dqs1<=1'b1;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
send_dqs1<=1'b0;
|
send_dqs1<=1'b0;
|
end
|
end
|
end
|
end
|
send_dqs0<=send_dqs1;
|
send_dqs0<=send_dqs1;
|
end//end always
|
end//end always
|
|
|
//ram here
|
//ram here
|
dport_ram #(
|
dport_ram #(
|
.DATA_WIDTH(8), //data_hi,data_lo
|
.DATA_WIDTH(8), //data_hi,data_lo
|
.ADDR_WIDTH(36)
|
.ADDR_WIDTH(36)
|
)dport_ram_hi(
|
)dport_ram_hi(
|
.clk (ck),
|
.clk (ck),
|
.di (data_hi),
|
.di (data_hi),
|
.read_addr (read_add+read_col),
|
.read_addr (read_add+read_col),
|
.write_addr (write_add+write_col),
|
.write_addr (write_add+write_col),
|
.we (mem_we & data_hi_dm),
|
.we (mem_we & data_hi_dm),
|
.do (read_data[15:8])
|
.do (read_data[15:8])
|
);
|
);
|
|
|
dport_ram #(
|
dport_ram #(
|
.DATA_WIDTH(8), //data_hi,data_lo
|
.DATA_WIDTH(8), //data_hi,data_lo
|
.ADDR_WIDTH(36)
|
.ADDR_WIDTH(36)
|
)dport_ram_lo(
|
)dport_ram_lo(
|
.clk (ck),
|
.clk (ck),
|
.di (data_lo),
|
.di (data_lo),
|
.read_addr (read_add+read_col),
|
.read_addr (read_add+read_col),
|
.write_addr (write_add+write_col),
|
.write_addr (write_add+write_col),
|
.we (mem_we & data_lo_dm),
|
.we (mem_we & data_lo_dm),
|
.do (read_data[7:0])
|
.do (read_data[7:0])
|
);
|
);
|
assign dqs =((send_dqs0==1'b1) || (send_dq==1'b1))?ck:1'bz;
|
assign dqs =((send_dqs0==1'b1) || (send_dq==1'b1))?ck:1'bz;
|
assign dqs_n=((send_dqs0==1'b1) || (send_dq==1'b1))?ck_n:1'bz;
|
assign dqs_n=((send_dqs0==1'b1) || (send_dq==1'b1))?ck_n:1'bz;
|
assign dq = (send_dq==1'b1)?dq_out:8'hZZ;
|
assign dq = (send_dq==1'b1)?dq_out:8'hZZ;
|
|
|
/* utility functions to display information
|
/* utility functions to display information
|
*/
|
*/
|
initial begin
|
initial begin
|
$timeformat (-9, 1, " ns", 1);
|
$timeformat (-9, 1, " ns", 1);
|
end
|
end
|
|
|
always @(posedge ck )
|
always @(posedge ck )
|
begin
|
begin
|
case({cs_n,ras_n,cas_n,we_n})
|
case({cs_n,ras_n,cas_n,we_n})
|
|
|
OPCODE_PRECHARGE :begin
|
OPCODE_PRECHARGE :begin
|
$display("%m: at time %t PRECHARGE ",$time);
|
$display("%m: at time %t PRECHARGE ",$time);
|
end
|
end
|
|
|
OPCODE_ACTIVATE :begin
|
OPCODE_ACTIVATE :begin
|
$display("%m: at time %t ACTIVATE - BANK[%x]\tROW[%x]",$time,ba,a);
|
$display("%m: at time %t ACTIVATE - BANK[%x]\tROW[%x]",$time,ba,a);
|
end
|
end
|
|
|
OPCODE_DES :begin
|
OPCODE_DES :begin
|
$display("%m: at time %t DES ",$time);
|
$display("%m: at time %t DES ",$time);
|
end
|
end
|
OPCODE_MRS :begin
|
OPCODE_MRS :begin
|
$display("%m: at time %t MRS ",$time);
|
$display("%m: at time %t MRS ",$time);
|
end
|
end
|
/*OPCODE_NOP :begin
|
/*OPCODE_NOP :begin
|
/$display("%m: at time %t WRITE ",$time);
|
/$display("%m: at time %t WRITE ",$time);
|
end
|
end
|
*/
|
*/
|
/*
|
/*
|
OPCODE_READ :begin
|
OPCODE_READ :begin
|
$display("%m: at time %t READ - BANK[%x]\tROW[%x]\tCOL[%x]",$time,ba,last_row,a);
|
$display("%m: at time %t READ - BANK[%x]\tROW[%x]\tCOL[%x]",$time,ba,last_row,a);
|
end
|
end
|
OPCODE_WRITE :begin
|
OPCODE_WRITE :begin
|
$display("%m: at time %t WRITE - BANK[%x]\tROW[%x],\tCOL[%x]",$time,ba,last_row,a);
|
$display("%m: at time %t WRITE - BANK[%x]\tROW[%x],\tCOL[%x]",$time,ba,last_row,a);
|
end
|
end
|
*/
|
*/
|
OPCODE_ZQC :begin
|
OPCODE_ZQC :begin
|
$display("%m: at time %t ZQC ",$time);
|
$display("%m: at time %t ZQC ",$time);
|
end
|
end
|
endcase
|
endcase
|
|
|
end // end always@(*)
|
end // end always@(*)
|
/* end utility*/
|
/* end utility*/
|
|
|
endmodule
|
endmodule
|
|
|
