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Subversion Repositories ddr3_synthesizable_bfm

[/] [ddr3_synthesizable_bfm/] [trunk/] [rtl/] [ddr3_simple4.v] - Diff between revs 6 and 7

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Rev 6 Rev 7
Line 37... Line 37...
module ddr3_simple4#(
module ddr3_simple4#(
parameter MEM_DQ_WIDTH          =8,
parameter MEM_DQ_WIDTH          =8,
parameter MEM_BA_WIDTH          =3,
parameter MEM_BA_WIDTH          =3,
parameter MEM_ROW_WIDTH         =13,
parameter MEM_ROW_WIDTH         =13,
parameter MEM_COL_WIDTH         =13,
parameter MEM_COL_WIDTH         =13,
parameter MEM_AL                =0,
parameter AL            =3,
parameter MEM_CWL               =8, //CWL
parameter CWL           =5, //CWL
parameter MEM_CL                =6  //CL
parameter CL            =5  //CL=6 -> pass
)(
)(
input wire [MEM_ROW_WIDTH-1:0]   a,
input wire [MEM_ROW_WIDTH-1:0]   a,
input wire [ MEM_BA_WIDTH-1:0]   ba,
input wire [ MEM_BA_WIDTH-1:0]   ba,
input wire                      ck,
input wire                      ck,
input wire                      ck_n,
input wire                      ck_n,
Line 59... Line 59...
inout wire                      dqs_n,
inout wire                      dqs_n,
input wire                      odt
input wire                      odt
);
);
 
 
//convert actual CL and CWL parameter to 
//convert actual CL and CWL parameter to 
 
localparam  MEM_CWL=CWL+AL;
 
localparam  MEM_CL =CL+AL;
 
 
//definitions
//definitions
localparam      OPCODE_PRECHARGE = 4'b0010;
localparam      OPCODE_PRECHARGE = 4'b0010;
localparam      OPCODE_ACTIVATE  = 4'b0011;
localparam      OPCODE_ACTIVATE  = 4'b0011;
localparam      OPCODE_WRITE     = 4'b0100;
localparam      OPCODE_WRITE     = 4'b0100;

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