/*single clock dual port ram
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/*single clock dual port ram
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2010-2011 sclai <laikos@yahoo.com>
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2010-2011 sclai <laikos@yahoo.com>
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This library is free software; you can redistribute it and/or modify it
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This library is free software; you can redistribute it and/or modify it
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under the terms of the GNU Lesser General Public License as published by
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under the terms of the GNU Lesser General Public License as published by
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the Free Software Foundation; either version 2.1 of the License,
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the Free Software Foundation; either version 2.1 of the License,
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or (at your option) any later version.
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or (at your option) any later version.
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This library is distributed in the hope that it will be useful, but
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This library is distributed in the hope that it will be useful, but
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WITHOUT ANY WARRANTY; without even the implied warranty of
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WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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You should have received a copy of the GNU Lesser General Public
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License along with this library; if not, write to the Free Software
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License along with this library; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
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Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
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USA
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USA
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Example:
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Example:
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Desity Bank Row Col
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Desity Bank Row Col
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-----------------------------
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-----------------------------
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64MB 2:0 12:0 9:0
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64MB 2:0 12:0 9:0
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128MB 2:0 13:0 9:0
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128MB 2:0 13:0 9:0
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512MB 2:0 13:0 10:0
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512MB 2:0 13:0 10:0
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1GB 2:0 15:0 10:0
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1GB 2:0 15:0 10:0
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*/
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*/
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module dport_ram
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module dport_ram
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#(
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#(
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parameter DATA_WIDTH=8,
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parameter DATA_WIDTH=8,
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parameter ADDR_WIDTH=36
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parameter ADDR_WIDTH=36
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)(
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)(
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input clk,
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input clk,
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input [(DATA_WIDTH-1):0] di,
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input [(DATA_WIDTH-1):0] di,
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input [(ADDR_WIDTH-1):0] read_addr,
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input [(ADDR_WIDTH-1):0] read_addr,
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input [(ADDR_WIDTH-1):0] write_addr,
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input [(ADDR_WIDTH-1):0] write_addr,
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input we,
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input we,
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output reg [(DATA_WIDTH-1):0] do
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output reg [(DATA_WIDTH-1):0] do
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);
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);
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//localparam ACTUAL_ADDR_WIDTH=16; //due to small size of internal memory
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localparam ACTUAL_ADDR_WIDTH=16; //due to small size of internal memory
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localparam ACTUAL_ADDR_WIDTH=26; //due to small size of internal memory
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//localparam ACTUAL_ADDR_WIDTH=26; //due to small size of internal memory
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wire [ACTUAL_ADDR_WIDTH-1:0]ACTUAL_WRITE_ADDR;
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wire [ACTUAL_ADDR_WIDTH-1:0]ACTUAL_WRITE_ADDR;
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wire [ACTUAL_ADDR_WIDTH-1:0]ACTUAL_READ_ADDR;
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wire [ACTUAL_ADDR_WIDTH-1:0]ACTUAL_READ_ADDR;
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//bank row col
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//bank row col
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//assign ACTUAL_WRITE_ADDR={write_addr[34:32],write_addr[25:16],write_addr[7:0]};
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//assign ACTUAL_WRITE_ADDR={write_addr[34:32],write_addr[25:16],write_addr[7:0]};
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//assign ACTUAL_READ_ADDR ={ read_addr[34:32], read_addr[25:16], read_addr[7:0]};
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//assign ACTUAL_READ_ADDR ={ read_addr[34:32], read_addr[25:16], read_addr[7:0]};
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assign ACTUAL_WRITE_ADDR={write_addr[34:32],write_addr[28:16],write_addr[9:0]};
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assign ACTUAL_WRITE_ADDR={write_addr[34:32],write_addr[28:16],write_addr[9:0]};
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assign ACTUAL_READ_ADDR ={ read_addr[34:32], read_addr[28:16], read_addr[9:0]};
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assign ACTUAL_READ_ADDR ={ read_addr[34:32], read_addr[28:16], read_addr[9:0]};
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//8196Kbytes RAM
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//8196Kbytes RAM
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reg [DATA_WIDTH-1:0] ram[2**ACTUAL_ADDR_WIDTH-1:0];
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reg [DATA_WIDTH-1:0] ram[2**ACTUAL_ADDR_WIDTH-1:0];
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always @ (posedge clk)
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always @ (posedge clk)
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begin
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begin
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if (we==1'b1)
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if (we==1'b1)
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begin
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begin
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ram[ACTUAL_WRITE_ADDR] <= di;
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ram[ACTUAL_WRITE_ADDR] <= di;
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end
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end
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else
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else
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begin
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begin
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do <= ram[ACTUAL_READ_ADDR];
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do <= ram[ACTUAL_READ_ADDR];
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end
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end
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end
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end
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endmodule
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endmodule
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