Release 13.1 - xst O.40d (nt)
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Release 13.1 - xst O.40d (nt)
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Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
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Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
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--> Parameter TMPDIR set to xst/projnav.tmp
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--> Parameter TMPDIR set to xst/projnav.tmp
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Total REAL time to Xst completion: 0.00 secs
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Total REAL time to Xst completion: 0.00 secs
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Total CPU time to Xst completion: 0.08 secs
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Total CPU time to Xst completion: 0.08 secs
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--> Parameter xsthdpdir set to xst
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--> Parameter xsthdpdir set to xst
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Total REAL time to Xst completion: 0.00 secs
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Total REAL time to Xst completion: 0.00 secs
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Total CPU time to Xst completion: 0.08 secs
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Total CPU time to Xst completion: 0.08 secs
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--> Reading design: debounce_atlys_top.prj
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--> Reading design: debounce_atlys_top.prj
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TABLE OF CONTENTS
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TABLE OF CONTENTS
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1) Synthesis Options Summary
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1) Synthesis Options Summary
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2) HDL Parsing
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2) HDL Parsing
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3) HDL Elaboration
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3) HDL Elaboration
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4) HDL Synthesis
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4) HDL Synthesis
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4.1) HDL Synthesis Report
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4.1) HDL Synthesis Report
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5) Advanced HDL Synthesis
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5) Advanced HDL Synthesis
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5.1) Advanced HDL Synthesis Report
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5.1) Advanced HDL Synthesis Report
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6) Low Level Synthesis
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6) Low Level Synthesis
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7) Partition Report
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7) Partition Report
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8) Design Summary
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8) Design Summary
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8.1) Primitive and Black Box Usage
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8.1) Primitive and Black Box Usage
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8.2) Device utilization summary
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8.2) Device utilization summary
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8.3) Partition Resource Summary
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8.3) Partition Resource Summary
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8.4) Timing Report
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8.4) Timing Report
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8.4.1) Clock Information
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8.4.1) Clock Information
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8.4.2) Asynchronous Control Signals Information
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8.4.2) Asynchronous Control Signals Information
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8.4.3) Timing Summary
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8.4.3) Timing Summary
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8.4.4) Timing Details
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8.4.4) Timing Details
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8.4.5) Cross Clock Domains Report
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8.4.5) Cross Clock Domains Report
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=========================================================================
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=========================================================================
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* Synthesis Options Summary *
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* Synthesis Options Summary *
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=========================================================================
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=========================================================================
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---- Source Parameters
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---- Source Parameters
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Input File Name : "debounce_atlys_top.prj"
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Input File Name : "debounce_atlys_top.prj"
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Input Format : mixed
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Input Format : mixed
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Ignore Synthesis Constraint File : NO
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Ignore Synthesis Constraint File : NO
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---- Target Parameters
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---- Target Parameters
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Output File Name : "debounce_atlys_top"
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Output File Name : "debounce_atlys_top"
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Output Format : NGC
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Output Format : NGC
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Target Device : xc6slx45-2-csg324
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Target Device : xc6slx45-2-csg324
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---- Source Options
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---- Source Options
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Top Module Name : debounce_atlys_top
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Top Module Name : debounce_atlys_top
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Automatic FSM Extraction : YES
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Automatic FSM Extraction : YES
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FSM Encoding Algorithm : Gray
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FSM Encoding Algorithm : Gray
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Safe Implementation : No
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Safe Implementation : No
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FSM Style : LUT
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FSM Style : LUT
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RAM Extraction : No
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RAM Extraction : No
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ROM Extraction : No
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ROM Extraction : No
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Shift Register Extraction : NO
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Shift Register Extraction : NO
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Resource Sharing : YES
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Resource Sharing : YES
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Asynchronous To Synchronous : NO
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Asynchronous To Synchronous : NO
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Shift Register Minimum Size : 2
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Shift Register Minimum Size : 2
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Use DSP Block : Auto
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Use DSP Block : Auto
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Automatic Register Balancing : No
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Automatic Register Balancing : No
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---- Target Options
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---- Target Options
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LUT Combining : Area
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LUT Combining : Area
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Reduce Control Sets : Auto
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Reduce Control Sets : Auto
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Add IO Buffers : YES
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Add IO Buffers : YES
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Global Maximum Fanout : 100000
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Global Maximum Fanout : 100000
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Add Generic Clock Buffer(BUFG) : 16
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Add Generic Clock Buffer(BUFG) : 16
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Register Duplication : YES
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Register Duplication : YES
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Optimize Instantiated Primitives : NO
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Optimize Instantiated Primitives : NO
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Use Clock Enable : Auto
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Use Clock Enable : Auto
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Use Synchronous Set : Auto
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Use Synchronous Set : Auto
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Use Synchronous Reset : Auto
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Use Synchronous Reset : Auto
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Pack IO Registers into IOBs : Auto
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Pack IO Registers into IOBs : Auto
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Equivalent register Removal : YES
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Equivalent register Removal : YES
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---- General Options
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---- General Options
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Optimization Goal : Speed
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Optimization Goal : Speed
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Optimization Effort : 2
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Optimization Effort : 2
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Power Reduction : NO
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Power Reduction : NO
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Keep Hierarchy : No
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Keep Hierarchy : No
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Netlist Hierarchy : As_Optimized
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Netlist Hierarchy : As_Optimized
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RTL Output : Yes
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RTL Output : Yes
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Global Optimization : AllClockNets
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Global Optimization : AllClockNets
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Read Cores : YES
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Read Cores : YES
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Write Timing Constraints : NO
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Write Timing Constraints : NO
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Cross Clock Analysis : NO
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Cross Clock Analysis : NO
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Hierarchy Separator : /
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Hierarchy Separator : /
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Bus Delimiter : <>
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Bus Delimiter : <>
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Case Specifier : Maintain
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Case Specifier : Maintain
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Slice Utilization Ratio : 100
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Slice Utilization Ratio : 100
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BRAM Utilization Ratio : 100
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BRAM Utilization Ratio : 100
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DSP48 Utilization Ratio : 100
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DSP48 Utilization Ratio : 100
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Auto BRAM Packing : NO
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Auto BRAM Packing : NO
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Slice Utilization Ratio Delta : 5
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Slice Utilization Ratio Delta : 5
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=========================================================================
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=========================================================================
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=========================================================================
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=========================================================================
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* HDL Parsing *
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* HDL Parsing *
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=========================================================================
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=========================================================================
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Parsing VHDL file "C:\dropbox\Dropbox\VHDL_training\OpenCores\debouncer_vhdl\debouncer_vhdl\trunk\bench\grp_debouncer.vhd" into library work
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Parsing VHDL file "C:\dropbox\Dropbox\VHDL_training\OpenCores\debouncer_vhdl\debouncer_vhdl\trunk\bench\grp_debouncer.vhd" into library work
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Parsing entity .
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Parsing entity .
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Parsing architecture of entity .
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Parsing architecture of entity .
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Parsing VHDL file "C:\dropbox\Dropbox\VHDL_training\OpenCores\debouncer_vhdl\debouncer_vhdl\trunk\bench\debounce_atlys_top.vhd" into library work
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Parsing VHDL file "C:\dropbox\Dropbox\VHDL_training\OpenCores\debouncer_vhdl\debouncer_vhdl\trunk\bench\debounce_atlys_top.vhd" into library work
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Parsing entity .
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Parsing entity .
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Parsing architecture of entity .
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Parsing architecture of entity .
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=========================================================================
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=========================================================================
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* HDL Elaboration *
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* HDL Elaboration *
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=========================================================================
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=========================================================================
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Elaborating entity (architecture ) from library .
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Elaborating entity (architecture ) from library .
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Elaborating entity (architecture ) with generics from library .
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Elaborating entity (architecture ) with generics from library .
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WARNING:HDLCompiler:634 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\debouncer_vhdl\debouncer_vhdl\trunk\bench\debounce_atlys_top.vhd" Line 71: Net does not have a driver.
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=========================================================================
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=========================================================================
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* HDL Synthesis *
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* HDL Synthesis *
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=========================================================================
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=========================================================================
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Synthesizing Unit .
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Synthesizing Unit .
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Related source file is "c:/dropbox/dropbox/vhdl_training/opencores/debouncer_vhdl/debouncer_vhdl/trunk/bench/debounce_atlys_top.vhd".
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Related source file is "c:/dropbox/dropbox/vhdl_training/opencores/debouncer_vhdl/debouncer_vhdl/trunk/bench/debounce_atlys_top.vhd".
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Found 8-bit register for signal .
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WARNING:Xst:2935 - Signal 'dbg<15>', unconnected in block 'debounce_atlys_top', is tied to its initial value (0).
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Found 7-bit register for signal .
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Summary:
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Summary:
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inferred 8 D-type flip-flop(s).
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inferred 7 D-type flip-flop(s).
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Unit synthesized.
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Unit synthesized.
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Synthesizing Unit .
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Synthesizing Unit .
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Related source file is "c:/dropbox/dropbox/vhdl_training/opencores/debouncer_vhdl/debouncer_vhdl/trunk/bench/grp_debouncer.vhd".
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Related source file is "c:/dropbox/dropbox/vhdl_training/opencores/debouncer_vhdl/debouncer_vhdl/trunk/bench/grp_debouncer.vhd".
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N = 8
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N = 7
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CNT_VAL = 5000
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CNT_VAL = 5000
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Found 8-bit register for signal .
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Found 7-bit register for signal .
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Found 8-bit register for signal .
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Found 7-bit register for signal .
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Found 1-bit register for signal .
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Found 1-bit register for signal .
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Found 8-bit register for signal .
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Found 7-bit register for signal .
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Found 13-bit register for signal .
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Found 13-bit register for signal .
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Found 14-bit adder for signal created at line 167.
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Found 14-bit adder for signal created at line 167.
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Found 8-bit comparator not equal for signal created at line 192
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Found 7-bit comparator not equal for signal created at line 192
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Found 8-bit comparator not equal for signal created at line 194
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Found 7-bit comparator not equal for signal created at line 194
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Summary:
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Summary:
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inferred 1 Adder/Subtractor(s).
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inferred 1 Adder/Subtractor(s).
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inferred 38 D-type flip-flop(s).
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inferred 35 D-type flip-flop(s).
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inferred 2 Comparator(s).
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inferred 2 Comparator(s).
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Unit synthesized.
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Unit synthesized.
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=========================================================================
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=========================================================================
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HDL Synthesis Report
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HDL Synthesis Report
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Macro Statistics
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Macro Statistics
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# Adders/Subtractors : 1
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# Adders/Subtractors : 1
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14-bit adder : 1
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14-bit adder : 1
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# Registers : 6
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# Registers : 6
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1-bit register : 1
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1-bit register : 1
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13-bit register : 1
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13-bit register : 1
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8-bit register : 4
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7-bit register : 4
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# Comparators : 2
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# Comparators : 2
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8-bit comparator not equal : 2
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7-bit comparator not equal : 2
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=========================================================================
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=========================================================================
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=========================================================================
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=========================================================================
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* Advanced HDL Synthesis *
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* Advanced HDL Synthesis *
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=========================================================================
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=========================================================================
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Synthesizing (advanced) Unit .
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Synthesizing (advanced) Unit .
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The following registers are absorbed into counter : 1 register on signal .
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The following registers are absorbed into counter : 1 register on signal .
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Unit synthesized (advanced).
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Unit synthesized (advanced).
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=========================================================================
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=========================================================================
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Advanced HDL Synthesis Report
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Advanced HDL Synthesis Report
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Macro Statistics
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Macro Statistics
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# Counters : 1
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# Counters : 1
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13-bit up counter : 1
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13-bit up counter : 1
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# Registers : 33
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# Registers : 29
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Flip-Flops : 33
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Flip-Flops : 29
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# Comparators : 2
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# Comparators : 2
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8-bit comparator not equal : 2
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7-bit comparator not equal : 2
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=========================================================================
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=========================================================================
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=========================================================================
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=========================================================================
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* Low Level Synthesis *
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* Low Level Synthesis *
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=========================================================================
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=========================================================================
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Optimizing unit ...
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Optimizing unit ...
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Optimizing unit ...
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Optimizing unit ...
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Mapping all equations...
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Mapping all equations...
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Building and optimizing final netlist ...
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Building and optimizing final netlist ...
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Found area constraint ratio of 100 (+ 5) on block debounce_atlys_top, actual ratio is 0.
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Found area constraint ratio of 100 (+ 5) on block debounce_atlys_top, actual ratio is 0.
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Final Macro Processing ...
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Final Macro Processing ...
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=========================================================================
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=========================================================================
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Final Register Report
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Final Register Report
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Macro Statistics
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Macro Statistics
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# Registers : 46
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# Registers : 42
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Flip-Flops : 46
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Flip-Flops : 42
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=========================================================================
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=========================================================================
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=========================================================================
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=========================================================================
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* Partition Report *
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* Partition Report *
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=========================================================================
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=========================================================================
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Partition Implementation Status
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Partition Implementation Status
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-------------------------------
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-------------------------------
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No Partitions were found in this design.
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No Partitions were found in this design.
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-------------------------------
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-------------------------------
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=========================================================================
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=========================================================================
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* Design Summary *
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* Design Summary *
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=========================================================================
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=========================================================================
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Top Level Output File Name : debounce_atlys_top.ngc
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Top Level Output File Name : debounce_atlys_top.ngc
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Primitive and Black Box Usage:
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Primitive and Black Box Usage:
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------------------------------
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------------------------------
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# BELS : 75
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# BELS : 73
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# GND : 1
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# GND : 1
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# INV : 1
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# INV : 1
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# LUT1 : 12
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# LUT1 : 12
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# LUT3 : 2
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# LUT3 : 1
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# LUT4 : 8
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# LUT4 : 9
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# LUT6 : 25
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# LUT6 : 23
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# MUXCY : 12
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# MUXCY : 12
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# VCC : 1
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# VCC : 1
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# XORCY : 13
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# XORCY : 13
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# FlipFlops/Latches : 46
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# FlipFlops/Latches : 42
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# FD : 30
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# FD : 28
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# FDE : 16
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# FDE : 14
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# Clock Buffers : 1
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# Clock Buffers : 1
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# BUFGP : 1
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# BUFGP : 1
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# IO Buffers : 33
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# IO Buffers : 30
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# IBUF : 8
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# IBUF : 7
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# OBUF : 25
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# OBUF : 23
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Device utilization summary:
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Device utilization summary:
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---------------------------
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---------------------------
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Selected Device : 6slx45csg324-2
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Selected Device : 6slx45csg324-2
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Slice Logic Utilization:
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Slice Logic Utilization:
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Number of Slice Registers: 46 out of 54576 0%
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Number of Slice Registers: 42 out of 54576 0%
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Number of Slice LUTs: 48 out of 27288 0%
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Number of Slice LUTs: 46 out of 27288 0%
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Number used as Logic: 48 out of 27288 0%
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Number used as Logic: 46 out of 27288 0%
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Slice Logic Distribution:
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Slice Logic Distribution:
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Number of LUT Flip Flop pairs used: 72
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Number of LUT Flip Flop pairs used: 67
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Number with an unused Flip Flop: 26 out of 72 36%
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Number with an unused Flip Flop: 25 out of 67 37%
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Number with an unused LUT: 24 out of 72 33%
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Number with an unused LUT: 21 out of 67 31%
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Number of fully used LUT-FF pairs: 22 out of 72 30%
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Number of fully used LUT-FF pairs: 21 out of 67 31%
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Number of unique control sets: 3
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Number of unique control sets: 3
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IO Utilization:
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IO Utilization:
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Number of IOs: 34
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Number of IOs: 31
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Number of bonded IOBs: 34 out of 218 15%
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Number of bonded IOBs: 31 out of 218 14%
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Specific Feature Utilization:
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Specific Feature Utilization:
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Number of BUFG/BUFGCTRLs: 1 out of 16 6%
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Number of BUFG/BUFGCTRLs: 1 out of 16 6%
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---------------------------
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---------------------------
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Partition Resource Summary:
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Partition Resource Summary:
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---------------------------
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---------------------------
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No Partitions were found in this design.
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No Partitions were found in this design.
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---------------------------
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---------------------------
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=========================================================================
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=========================================================================
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Timing Report
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Timing Report
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NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
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NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
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FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
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FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
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GENERATED AFTER PLACE-and-ROUTE.
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GENERATED AFTER PLACE-and-ROUTE.
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Clock Information:
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Clock Information:
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------------------
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------------------
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-----------------------------------+------------------------+-------+
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-----------------------------------+------------------------+-------+
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Clock Signal | Clock buffer(FF name) | Load |
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Clock Signal | Clock buffer(FF name) | Load |
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-----------------------------------+------------------------+-------+
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-----------------------------------+------------------------+-------+
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gclk_i | BUFGP | 46 |
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gclk_i | BUFGP | 42 |
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-----------------------------------+------------------------+-------+
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-----------------------------------+------------------------+-------+
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Asynchronous Control Signals Information:
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Asynchronous Control Signals Information:
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----------------------------------------
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----------------------------------------
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No asynchronous control signals found in this design
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No asynchronous control signals found in this design
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Timing Summary:
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Timing Summary:
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---------------
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---------------
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Speed Grade: -2
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Speed Grade: -2
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Minimum period: 4.749ns (Maximum Frequency: 210.571MHz)
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Minimum period: 4.717ns (Maximum Frequency: 211.999MHz)
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Minimum input arrival time before clock: 2.127ns
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Minimum input arrival time before clock: 2.127ns
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Maximum output required time after clock: 4.412ns
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Maximum output required time after clock: 4.380ns
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Maximum combinational path delay: 4.965ns
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Maximum combinational path delay: 4.965ns
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Timing Details:
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Timing Details:
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---------------
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---------------
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All values displayed in nanoseconds (ns)
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All values displayed in nanoseconds (ns)
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=========================================================================
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=========================================================================
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Timing constraint: Default period analysis for Clock 'gclk_i'
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Timing constraint: Default period analysis for Clock 'gclk_i'
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Clock period: 4.749ns (frequency: 210.571MHz)
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Clock period: 4.717ns (frequency: 211.999MHz)
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Total number of paths / destination ports: 761 / 54
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Total number of paths / destination ports: 713 / 49
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-------------------------------------------------------------------------
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-------------------------------------------------------------------------
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Delay: 4.749ns (Levels of Logic = 3)
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Delay: 4.717ns (Levels of Logic = 3)
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Source: Inst_sw_debouncer/cnt_reg_0 (FF)
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Source: Inst_sw_debouncer/cnt_reg_0 (FF)
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Destination: Inst_sw_debouncer/strb_reg (FF)
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Destination: Inst_sw_debouncer/strb_reg (FF)
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Source Clock: gclk_i rising
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Source Clock: gclk_i rising
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Destination Clock: gclk_i rising
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Destination Clock: gclk_i rising
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Data Path: Inst_sw_debouncer/cnt_reg_0 to Inst_sw_debouncer/strb_reg
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Data Path: Inst_sw_debouncer/cnt_reg_0 to Inst_sw_debouncer/strb_reg
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Gate Net
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Gate Net
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Cell:in->out fanout Delay Delay Logical Name (Net Name)
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Cell:in->out fanout Delay Delay Logical Name (Net Name)
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---------------------------------------- ------------
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---------------------------------------- ------------
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FD:C->Q 2 0.525 1.181 Inst_sw_debouncer/cnt_reg_0 (Inst_sw_debouncer/cnt_reg_0)
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FD:C->Q 2 0.525 1.181 Inst_sw_debouncer/cnt_reg_0 (Inst_sw_debouncer/cnt_reg_0)
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LUT6:I0->O 9 0.254 1.084 Inst_sw_debouncer/dat_strb<12>1 (Inst_sw_debouncer/dat_strb<12>)
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LUT6:I0->O 8 0.254 1.052 Inst_sw_debouncer/dat_strb<12>1 (Inst_sw_debouncer/dat_strb<12>)
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LUT3:I1->O 14 0.250 1.127 Inst_sw_debouncer/dat_strb<12>3 (Inst_sw_debouncer/dat_strb)
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LUT3:I1->O 14 0.250 1.127 Inst_sw_debouncer/dat_strb<12>3 (Inst_sw_debouncer/dat_strb)
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LUT6:I5->O 1 0.254 0.000 Inst_sw_debouncer/strb_next7 (Inst_sw_debouncer/strb_next)
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LUT6:I5->O 1 0.254 0.000 Inst_sw_debouncer/strb_next6 (Inst_sw_debouncer/strb_next)
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FD:D 0.074 Inst_sw_debouncer/strb_reg
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FD:D 0.074 Inst_sw_debouncer/strb_reg
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----------------------------------------
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----------------------------------------
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Total 4.749ns (1.357ns logic, 3.392ns route)
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Total 4.717ns (1.357ns logic, 3.360ns route)
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(28.6% logic, 71.4% route)
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(28.8% logic, 71.2% route)
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=========================================================================
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=========================================================================
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Timing constraint: Default OFFSET IN BEFORE for Clock 'gclk_i'
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Timing constraint: Default OFFSET IN BEFORE for Clock 'gclk_i'
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Total number of paths / destination ports: 8 / 8
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Total number of paths / destination ports: 7 / 7
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-------------------------------------------------------------------------
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-------------------------------------------------------------------------
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Offset: 2.127ns (Levels of Logic = 1)
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Offset: 2.127ns (Levels of Logic = 1)
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Source: sw_i<7> (PAD)
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Source: sw_i<6> (PAD)
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Destination: Inst_sw_debouncer/reg_A_7 (FF)
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Destination: Inst_sw_debouncer/reg_A_6 (FF)
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Destination Clock: gclk_i rising
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Destination Clock: gclk_i rising
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Data Path: sw_i<7> to Inst_sw_debouncer/reg_A_7
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Data Path: sw_i<6> to Inst_sw_debouncer/reg_A_6
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Gate Net
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Gate Net
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Cell:in->out fanout Delay Delay Logical Name (Net Name)
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Cell:in->out fanout Delay Delay Logical Name (Net Name)
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---------------------------------------- ------------
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---------------------------------------- ------------
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IBUF:I->O 2 1.328 0.725 sw_i_7_IBUF (dbg_o_7_OBUF)
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IBUF:I->O 2 1.328 0.725 sw_i_6_IBUF (dbg_o_6_OBUF)
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FD:D 0.074 Inst_sw_debouncer/reg_A_7
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FD:D 0.074 Inst_sw_debouncer/reg_A_6
|
----------------------------------------
|
----------------------------------------
|
Total 2.127ns (1.402ns logic, 0.725ns route)
|
Total 2.127ns (1.402ns logic, 0.725ns route)
|
(65.9% logic, 34.1% route)
|
(65.9% logic, 34.1% route)
|
|
|
=========================================================================
|
=========================================================================
|
Timing constraint: Default OFFSET OUT AFTER for Clock 'gclk_i'
|
Timing constraint: Default OFFSET OUT AFTER for Clock 'gclk_i'
|
Total number of paths / destination ports: 17 / 17
|
Total number of paths / destination ports: 15 / 15
|
-------------------------------------------------------------------------
|
-------------------------------------------------------------------------
|
Offset: 4.412ns (Levels of Logic = 1)
|
Offset: 4.380ns (Levels of Logic = 1)
|
Source: Inst_sw_debouncer/strb_reg (FF)
|
Source: Inst_sw_debouncer/strb_reg (FF)
|
Destination: strb_o (PAD)
|
Destination: dbg_o<14> (PAD)
|
Source Clock: gclk_i rising
|
Source Clock: gclk_i rising
|
|
|
Data Path: Inst_sw_debouncer/strb_reg to strb_o
|
Data Path: Inst_sw_debouncer/strb_reg to dbg_o<14>
|
Gate Net
|
Gate Net
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
---------------------------------------- ------------
|
---------------------------------------- ------------
|
FD:C->Q 9 0.525 0.975 Inst_sw_debouncer/strb_reg (Inst_sw_debouncer/strb_reg)
|
FD:C->Q 8 0.525 0.943 Inst_sw_debouncer/strb_reg (Inst_sw_debouncer/strb_reg)
|
OBUF:I->O 2.912 strb_o_OBUF (strb_o)
|
OBUF:I->O 2.912 dbg_o_14_OBUF (dbg_o<14>)
|
----------------------------------------
|
----------------------------------------
|
Total 4.412ns (3.437ns logic, 0.975ns route)
|
Total 4.380ns (3.437ns logic, 0.943ns route)
|
(77.9% logic, 22.1% route)
|
(78.5% logic, 21.5% route)
|
|
|
=========================================================================
|
=========================================================================
|
Timing constraint: Default path analysis
|
Timing constraint: Default path analysis
|
Total number of paths / destination ports: 8 / 8
|
Total number of paths / destination ports: 7 / 7
|
-------------------------------------------------------------------------
|
-------------------------------------------------------------------------
|
Delay: 4.965ns (Levels of Logic = 2)
|
Delay: 4.965ns (Levels of Logic = 2)
|
Source: sw_i<7> (PAD)
|
Source: sw_i<6> (PAD)
|
Destination: dbg_o<7> (PAD)
|
Destination: dbg_o<6> (PAD)
|
|
|
Data Path: sw_i<7> to dbg_o<7>
|
Data Path: sw_i<6> to dbg_o<6>
|
Gate Net
|
Gate Net
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
---------------------------------------- ------------
|
---------------------------------------- ------------
|
IBUF:I->O 2 1.328 0.725 sw_i_7_IBUF (dbg_o_7_OBUF)
|
IBUF:I->O 2 1.328 0.725 sw_i_6_IBUF (dbg_o_6_OBUF)
|
OBUF:I->O 2.912 dbg_o_7_OBUF (dbg_o<7>)
|
OBUF:I->O 2.912 dbg_o_6_OBUF (dbg_o<6>)
|
----------------------------------------
|
----------------------------------------
|
Total 4.965ns (4.240ns logic, 0.725ns route)
|
Total 4.965ns (4.240ns logic, 0.725ns route)
|
(85.4% logic, 14.6% route)
|
(85.4% logic, 14.6% route)
|
|
|
=========================================================================
|
=========================================================================
|
|
|
Cross Clock Domains Report:
|
Cross Clock Domains Report:
|
--------------------------
|
--------------------------
|
|
|
Clock to Setup on destination clock gclk_i
|
Clock to Setup on destination clock gclk_i
|
---------------+---------+---------+---------+---------+
|
---------------+---------+---------+---------+---------+
|
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
|
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
|
---------------+---------+---------+---------+---------+
|
---------------+---------+---------+---------+---------+
|
gclk_i | 4.749| | | |
|
gclk_i | 4.717| | | |
|
---------------+---------+---------+---------+---------+
|
---------------+---------+---------+---------+---------+
|
|
|
=========================================================================
|
=========================================================================
|
|
|
|
|
Total REAL time to Xst completion: 4.00 secs
|
Total REAL time to Xst completion: 4.00 secs
|
Total CPU time to Xst completion: 3.87 secs
|
Total CPU time to Xst completion: 4.57 secs
|
|
|
-->
|
-->
|
|
|
Total memory usage is 188424 kilobytes
|
Total memory usage is 185320 kilobytes
|
|
|
Number of errors : 0 ( 0 filtered)
|
Number of errors : 0 ( 0 filtered)
|
Number of warnings : 0 ( 0 filtered)
|
Number of warnings : 2 ( 0 filtered)
|
Number of infos : 0 ( 0 filtered)
|
Number of infos : 0 ( 0 filtered)
|
|
|
|
|
