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Release 13.1 Trace (nt)
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Release 13.1 Trace (nt)
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Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
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Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
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C:\Xilinx\13.1\ISE_DS\ISE\bin\nt\unwrapped\trce.exe -intstyle ise -v 3 -s 2 -n
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C:\Xilinx\13.1\ISE_DS\ISE\bin\nt\unwrapped\trce.exe -intstyle ise -v 3 -s 2 -n
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3 -fastpaths -xml debounce_atlys_top.twx debounce_atlys_top.ncd -o
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3 -fastpaths -xml debounce_atlys_top.twx debounce_atlys_top.ncd -o
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debounce_atlys_top.twr debounce_atlys_top.pcf -ucf debounce_atlys.ucf
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debounce_atlys_top.twr debounce_atlys_top.pcf -ucf debounce_atlys.ucf
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Design file: debounce_atlys_top.ncd
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Design file: debounce_atlys_top.ncd
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Physical constraint file: debounce_atlys_top.pcf
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Physical constraint file: debounce_atlys_top.pcf
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Device,package,speed: xc6slx45,csg324,C,-2 (PRODUCTION 1.18 2011-04-07)
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Device,package,speed: xc6slx45,csg324,C,-2 (PRODUCTION 1.18 2011-04-07)
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Report level: verbose report
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Report level: verbose report
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Environment Variable Effect
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Environment Variable Effect
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-------------------- ------
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-------------------- ------
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NONE No environment variables were set
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NONE No environment variables were set
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INFO:Timing:2698 - No timing constraints found, doing default enumeration.
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INFO:Timing:2698 - No timing constraints found, doing default enumeration.
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INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
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INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
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option. All paths that are not constrained will be reported in the
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option. All paths that are not constrained will be reported in the
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unconstrained paths section(s) of the report.
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unconstrained paths section(s) of the report.
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INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
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INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
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a 50 Ohm transmission line loading model. For the details of this model,
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a 50 Ohm transmission line loading model. For the details of this model,
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and for more information on accounting for different loading conditions,
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and for more information on accounting for different loading conditions,
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please see the device datasheet.
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please see the device datasheet.
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Data Sheet report:
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Data Sheet report:
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-----------------
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-----------------
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All values displayed in nanoseconds (ns)
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All values displayed in nanoseconds (ns)
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Setup/Hold to clock gclk_i
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Setup/Hold to clock gclk_i
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------------+------------+------------+------------+------------+------------------+--------+
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------------+------------+------------+------------+------------+------------------+--------+
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|Max Setup to| Process |Max Hold to | Process | | Clock |
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|Max Setup to| Process |Max Hold to | Process | | Clock |
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Source | clk (edge) | Corner | clk (edge) | Corner |Internal Clock(s) | Phase |
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Source | clk (edge) | Corner | clk (edge) | Corner |Internal Clock(s) | Phase |
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------------+------------+------------+------------+------------+------------------+--------+
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------------+------------+------------+------------+------------+------------------+--------+
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sw_i<0> | 5.038(R)| SLOW | -2.761(R)| FAST |gclk_i_BUFGP | 0.000|
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sw_i<0> | 4.897(R)| SLOW | -2.640(R)| FAST |gclk_i_BUFGP | 0.000|
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sw_i<1> | 5.576(R)| SLOW | -3.098(R)| FAST |gclk_i_BUFGP | 0.000|
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sw_i<1> | 5.976(R)| SLOW | -3.369(R)| FAST |gclk_i_BUFGP | 0.000|
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sw_i<2> | 5.317(R)| SLOW | -2.953(R)| FAST |gclk_i_BUFGP | 0.000|
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sw_i<2> | 6.081(R)| SLOW | -3.407(R)| FAST |gclk_i_BUFGP | 0.000|
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sw_i<3> | 4.491(R)| SLOW | -2.388(R)| FAST |gclk_i_BUFGP | 0.000|
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sw_i<3> | 5.313(R)| SLOW | -2.891(R)| FAST |gclk_i_BUFGP | 0.000|
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sw_i<4> | 2.742(R)| SLOW | -1.466(R)| FAST |gclk_i_BUFGP | 0.000|
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sw_i<4> | 2.578(R)| SLOW | -1.340(R)| SLOW |gclk_i_BUFGP | 0.000|
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sw_i<5> | 4.819(R)| SLOW | -2.715(R)| FAST |gclk_i_BUFGP | 0.000|
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sw_i<5> | 3.922(R)| SLOW | -2.152(R)| FAST |gclk_i_BUFGP | 0.000|
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sw_i<6> | 4.336(R)| SLOW | -2.454(R)| FAST |gclk_i_BUFGP | 0.000|
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sw_i<6> | 3.293(R)| SLOW | -1.813(R)| FAST |gclk_i_BUFGP | 0.000|
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sw_i<7> | 5.893(R)| SLOW | -3.333(R)| FAST |gclk_i_BUFGP | 0.000|
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------------+------------+------------+------------+------------+------------------+--------+
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------------+------------+------------+------------+------------+------------------+--------+
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Clock gclk_i to Pad
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Clock gclk_i to Pad
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------------+-----------------+------------+-----------------+------------+------------------+--------+
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------------+-----------------+------------+-----------------+------------+------------------+--------+
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|Max (slowest) clk| Process |Min (fastest) clk| Process | | Clock |
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|Max (slowest) clk| Process |Min (fastest) clk| Process | | Clock |
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Destination | (edge) to PAD | Corner | (edge) to PAD | Corner |Internal Clock(s) | Phase |
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Destination | (edge) to PAD | Corner | (edge) to PAD | Corner |Internal Clock(s) | Phase |
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------------+-----------------+------------+-----------------+------------+------------------+--------+
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------------+-----------------+------------+-----------------+------------+------------------+--------+
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dbg_o<8> | 11.232(R)| SLOW | 4.814(R)| FAST |gclk_i_BUFGP | 0.000|
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dbg_o<7> | 11.316(R)| SLOW | 4.892(R)| FAST |gclk_i_BUFGP | 0.000|
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dbg_o<9> | 11.480(R)| SLOW | 4.979(R)| FAST |gclk_i_BUFGP | 0.000|
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dbg_o<8> | 11.472(R)| SLOW | 4.944(R)| FAST |gclk_i_BUFGP | 0.000|
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dbg_o<10> | 11.254(R)| SLOW | 4.861(R)| FAST |gclk_i_BUFGP | 0.000|
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dbg_o<9> | 11.204(R)| SLOW | 4.794(R)| FAST |gclk_i_BUFGP | 0.000|
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dbg_o<11> | 11.049(R)| SLOW | 4.732(R)| FAST |gclk_i_BUFGP | 0.000|
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dbg_o<10> | 11.504(R)| SLOW | 4.993(R)| FAST |gclk_i_BUFGP | 0.000|
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dbg_o<12> | 11.559(R)| SLOW | 5.013(R)| FAST |gclk_i_BUFGP | 0.000|
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dbg_o<11> | 11.865(R)| SLOW | 5.220(R)| FAST |gclk_i_BUFGP | 0.000|
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dbg_o<13> | 11.939(R)| SLOW | 5.209(R)| FAST |gclk_i_BUFGP | 0.000|
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dbg_o<12> | 12.635(R)| SLOW | 5.653(R)| FAST |gclk_i_BUFGP | 0.000|
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dbg_o<14> | 12.377(R)| SLOW | 5.519(R)| FAST |gclk_i_BUFGP | 0.000|
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dbg_o<13> | 12.428(R)| SLOW | 5.522(R)| FAST |gclk_i_BUFGP | 0.000|
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dbg_o<15> | 12.060(R)| SLOW | 5.330(R)| FAST |gclk_i_BUFGP | 0.000|
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dbg_o<14> | 13.576(R)| SLOW | 6.221(R)| FAST |gclk_i_BUFGP | 0.000|
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led_o<0> | 9.814(R)| SLOW | 4.065(R)| FAST |gclk_i_BUFGP | 0.000|
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led_o<0> | 9.204(R)| SLOW | 3.688(R)| FAST |gclk_i_BUFGP | 0.000|
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led_o<1> | 9.656(R)| SLOW | 3.955(R)| FAST |gclk_i_BUFGP | 0.000|
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led_o<1> | 9.148(R)| SLOW | 3.672(R)| FAST |gclk_i_BUFGP | 0.000|
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led_o<2> | 9.469(R)| SLOW | 3.865(R)| FAST |gclk_i_BUFGP | 0.000|
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led_o<2> | 9.367(R)| SLOW | 3.814(R)| FAST |gclk_i_BUFGP | 0.000|
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led_o<3> | 9.929(R)| SLOW | 4.132(R)| FAST |gclk_i_BUFGP | 0.000|
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led_o<3> | 9.812(R)| SLOW | 4.033(R)| FAST |gclk_i_BUFGP | 0.000|
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led_o<4> | 9.577(R)| SLOW | 3.889(R)| FAST |gclk_i_BUFGP | 0.000|
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led_o<4> | 10.245(R)| SLOW | 4.270(R)| FAST |gclk_i_BUFGP | 0.000|
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led_o<5> | 17.272(R)| SLOW | 8.413(R)| FAST |gclk_i_BUFGP | 0.000|
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led_o<5> | 16.830(R)| SLOW | 8.118(R)| FAST |gclk_i_BUFGP | 0.000|
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led_o<6> | 11.323(R)| SLOW | 4.861(R)| FAST |gclk_i_BUFGP | 0.000|
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led_o<6> | 11.879(R)| SLOW | 5.161(R)| FAST |gclk_i_BUFGP | 0.000|
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led_o<7> | 10.605(R)| SLOW | 4.453(R)| FAST |gclk_i_BUFGP | 0.000|
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strb_o | 13.397(R)| SLOW | 6.237(R)| FAST |gclk_i_BUFGP | 0.000|
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------------+-----------------+------------+-----------------+------------+------------------+--------+
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------------+-----------------+------------+-----------------+------------+------------------+--------+
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Clock to Setup on destination clock gclk_i
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Clock to Setup on destination clock gclk_i
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---------------+---------+---------+---------+---------+
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---------------+---------+---------+---------+---------+
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| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
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| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
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Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
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Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
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---------------+---------+---------+---------+---------+
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---------------+---------+---------+---------+---------+
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gclk_i | 4.464| | | |
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gclk_i | 4.423| | | |
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---------------+---------+---------+---------+---------+
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---------------+---------+---------+---------+---------+
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Pad to Pad
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Pad to Pad
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---------------+---------------+---------+
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---------------+---------------+---------+
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Source Pad |Destination Pad| Delay |
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Source Pad |Destination Pad| Delay |
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---------------+---------------+---------+
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---------------+---------------+---------+
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sw_i<0> |dbg_o<0> | 16.209|
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sw_i<0> |dbg_o<0> | 15.462|
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sw_i<1> |dbg_o<1> | 16.941|
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sw_i<1> |dbg_o<1> | 16.552|
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sw_i<2> |dbg_o<2> | 16.803|
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sw_i<2> |dbg_o<2> | 16.755|
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sw_i<3> |dbg_o<3> | 9.229|
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sw_i<3> |dbg_o<3> | 9.229|
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sw_i<4> |dbg_o<4> | 7.980|
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sw_i<4> |dbg_o<4> | 7.978|
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sw_i<5> |dbg_o<5> | 8.917|
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sw_i<5> |dbg_o<5> | 8.889|
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sw_i<6> |dbg_o<6> | 9.026|
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sw_i<6> |dbg_o<6> | 9.058|
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sw_i<7> |dbg_o<7> | 15.558|
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---------------+---------------+---------+
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---------------+---------------+---------+
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Analysis completed Thu Aug 11 00:07:33 2011
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Analysis completed Thu Aug 11 21:32:01 2011
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--------------------------------------------------------------------------------
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Trace Settings:
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Trace Settings:
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-------------------------
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-------------------------
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Trace Settings
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Trace Settings
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Peak Memory Usage: 178 MB
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Peak Memory Usage: 175 MB
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