| Line 36... |
Line 36... |
<TR ALIGN=LEFT>
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<TR ALIGN=LEFT>
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<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD>
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<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD>
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<TD><A HREF_DISABLED='Xilinx Default (unlocked)?&DataKey=Strategy'>Xilinx Default (unlocked)</A></TD>
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<TD><A HREF_DISABLED='Xilinx Default (unlocked)?&DataKey=Strategy'>Xilinx Default (unlocked)</A></TD>
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<TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD>
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<TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD>
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<TD>
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<TD>
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<A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top.ptwx?&DataKey=ConstraintsData'>All Constraints Met</A></TD>
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<A HREF_DISABLED='D:/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top.ptwx?&DataKey=ConstraintsData'>All Constraints Met</A></TD>
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</TR>
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</TR>
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<TR ALIGN=LEFT>
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<TR ALIGN=LEFT>
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<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD>
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<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD>
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<TD> </TD>
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<TD> </TD>
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<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD>
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<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD>
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| Line 191... |
Line 191... |
<TD ALIGN=RIGHT>6</TD>
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<TD ALIGN=RIGHT>6</TD>
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<TD ALIGN=RIGHT>54,576</TD>
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<TD ALIGN=RIGHT>54,576</TD>
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<TD ALIGN=RIGHT>1%</TD>
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<TD ALIGN=RIGHT>1%</TD>
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<TD COLSPAN='2'> </TD>
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<TD COLSPAN='2'> </TD>
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</TR>
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of bonded <A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top_map.xrpt?&DataKey=IOBProperties'>IOBs</A></TD>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of bonded <A HREF_DISABLED='D:/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top_map.xrpt?&DataKey=IOBProperties'>IOBs</A></TD>
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<TD ALIGN=RIGHT>31</TD>
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<TD ALIGN=RIGHT>31</TD>
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<TD ALIGN=RIGHT>218</TD>
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<TD ALIGN=RIGHT>218</TD>
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<TD ALIGN=RIGHT>14%</TD>
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<TD ALIGN=RIGHT>14%</TD>
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<TD COLSPAN='2'> </TD>
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<TD COLSPAN='2'> </TD>
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</TR>
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</TR>
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| Line 357... |
Line 357... |
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='4'><B>Performance Summary</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=PerformanceSummary"><B>[-]</B></a></TD></TR>
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<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='4'><B>Performance Summary</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=PerformanceSummary"><B>[-]</B></a></TD></TR>
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<TR ALIGN=LEFT>
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<TR ALIGN=LEFT>
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<TD BGCOLOR='#FFFF99'><B>Final Timing Score:</B></TD>
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<TD BGCOLOR='#FFFF99'><B>Final Timing Score:</B></TD>
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<TD>0 (Setup: 0, Hold: 0)</TD>
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<TD>0 (Setup: 0, Hold: 0)</TD>
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<TD BGCOLOR='#FFFF99'><B>Pinout Data:</B></TD>
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<TD BGCOLOR='#FFFF99'><B>Pinout Data:</B></TD>
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<TD COLSPAN='2'><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top_par.xrpt?&DataKey=PinoutData'>Pinout Report</A></TD>
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<TD COLSPAN='2'><A HREF_DISABLED='D:/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top_par.xrpt?&DataKey=PinoutData'>Pinout Report</A></TD>
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</TR>
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</TR>
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<TR ALIGN=LEFT>
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<TR ALIGN=LEFT>
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<TD BGCOLOR='#FFFF99'><B>Routing Results:</B></TD><TD>
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<TD BGCOLOR='#FFFF99'><B>Routing Results:</B></TD><TD>
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All Signals Completely Routed</TD>
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All Signals Completely Routed</TD>
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<TD BGCOLOR='#FFFF99'><B>Clock Data:</B></TD>
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<TD BGCOLOR='#FFFF99'><B>Clock Data:</B></TD>
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<TD COLSPAN='2'><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top_par.xrpt?&DataKey=ClocksData'>Clock Report</A></TD>
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<TD COLSPAN='2'><A HREF_DISABLED='D:/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top_par.xrpt?&DataKey=ClocksData'>Clock Report</A></TD>
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</TR>
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</TR>
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<TR ALIGN=LEFT>
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<TR ALIGN=LEFT>
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<TD BGCOLOR='#FFFF99'><B>Timing Constraints:</B></TD>
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<TD BGCOLOR='#FFFF99'><B>Timing Constraints:</B></TD>
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<TD>
|
<TD>
|
<A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top.ptwx?&DataKey=ConstraintsData'>All Constraints Met</A></TD>
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<A HREF_DISABLED='D:/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top.ptwx?&DataKey=ConstraintsData'>All Constraints Met</A></TD>
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<TD BGCOLOR='#FFFF99'><B> </B></TD>
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<TD BGCOLOR='#FFFF99'><B> </B></TD>
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<TD COLSPAN='2'> </TD>
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<TD COLSPAN='2'> </TD>
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</TABLE>
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</TABLE>
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<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
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<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
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<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
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<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
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<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
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<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
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<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
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<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
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<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Mon Aug 15 23:25:02 2011</TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
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<TR ALIGN=LEFT><TD><A HREF_DISABLED='D:/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>seg 15. ago 23:25:02 2011</TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
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<TR ALIGN=LEFT><TD>Translation Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
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<TR ALIGN=LEFT><TD>Translation Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
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<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>Mon Aug 15 23:25:36 2011</TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
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<TR ALIGN=LEFT><TD><A HREF_DISABLED='D:/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>seg 15. ago 23:25:36 2011</TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
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<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top.par'>Place and Route Report</A></TD><TD>Current</TD><TD>Mon Aug 15 23:25:47 2011</TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
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<TR ALIGN=LEFT><TD><A HREF_DISABLED='D:/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top.par'>Place and Route Report</A></TD><TD>Current</TD><TD>seg 15. ago 23:25:47 2011</TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
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<TR ALIGN=LEFT><TD>Power Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
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<TR ALIGN=LEFT><TD>Power Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
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<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top.twr'>Post-PAR Static Timing Report</A></TD><TD>Current</TD><TD>Mon Aug 15 23:25:54 2011</TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
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<TR ALIGN=LEFT><TD><A HREF_DISABLED='D:/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top.twr'>Post-PAR Static Timing Report</A></TD><TD>Current</TD><TD>seg 15. ago 23:25:54 2011</TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
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<TR ALIGN=LEFT><TD>Bitgen Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
|
<TR ALIGN=LEFT><TD>Bitgen Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
|
</TABLE>
|
</TABLE>
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<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
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<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
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<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
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<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
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<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
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<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
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<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top_map.psr'>Physical Synthesis Report</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Mon Aug 15 23:25:35 2011</TD></TR>
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<TR ALIGN=LEFT><TD><A HREF_DISABLED='D:/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\isim.log'>ISIM Simulator Log</A></TD><TD>Current</TD><TD COLSPAN='2'>seg 19. set 14:56:36 2011</TD></TR>
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<TR ALIGN=LEFT><TD><A HREF_DISABLED='D:/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top_map.psr'>Physical Synthesis Report</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>qui 11. ago 21:31:43 2011</TD></TR>
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</TABLE>
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</TABLE>
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<br><center><b>Date Generated:</b> 08/30/2011 - 11:26:47</center>
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<br><center><b>Date Generated:</b> 09/19/2011 - 15:37:38</center>
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