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----------------------------------------------------------------------------------
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-- Company:
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-- Copyright (c) 2013 Antonio de la Piedra
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-- Engineer:
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--
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-- This program is free software: you can redistribute it and/or modify
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-- Create Date: 09:30:59 02/20/2013
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-- it under the terms of the GNU General Public License as published by
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-- Design Name:
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-- the Free Software Foundation, either version 3 of the License, or
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-- Module Name: des - Behavioral
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-- (at your option) any later version.
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-- Project Name:
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-- Target Devices:
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-- This program is distributed in the hope that it will be useful,
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-- Tool versions:
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- Description:
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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--
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-- GNU General Public License for more details.
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-- Dependencies:
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--
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-- You should have received a copy of the GNU General Public License
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-- Revision:
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity des_loop is
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entity des_loop is
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port(clk : in std_logic;
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port(clk : in std_logic;
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rst : in std_logic;
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rst : in std_logic;
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mode : in std_logic; -- 0 encrypt, 1 decrypt
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mode : in std_logic; -- 0 encrypt, 1 decrypt
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key_in : in std_logic_vector(63 downto 0);
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key_in : in std_logic_vector(63 downto 0);
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if rising_edge(clk) then
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if rising_edge(clk) then
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rst_s <= rst;
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rst_s <= rst;
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end if;
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end if;
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end process;
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end process;
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-- k_0_s <= "101000001001001011000010000010101011000101000000";
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-- k_1_s <= "101000000001001001010010010011000000000010101011";
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-- k_2_s <= "001001000101101001010000000001100101100001001001";
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-- k_3_s <= "000001100111000101010000000000101001000101110000";
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-- k_4_s <= "000011100100010101010001100000011000110100100000";
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-- k_5_s <= "010011110100000100001001010010000000111000010000";
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-- k_6_s <= "000010111000000110001001010110010100000000011100";
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-- k_7_s <= "000110010000100010001011000000010101000010001000";
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-- k_8_s <= "000110010000101010001000000110000010111010010000";
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-- k_9_s <= "000100000011100010001100001110010100000000010001";
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-- k_10_s <= "000100000010110001000100000000110110000000000010";
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-- k_11_s <= "010000000110110000100100101001000010000100000100";
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-- k_12_s <= "110000001010010100100100101000000000001011000110";
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-- k_13_s <= "110000001000011000100011010101001000001010000011";
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-- k_14_s <= "111000011001001000100010000101100000010001001001";
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-- k_15_s <= "101000001001001000101010011000000001010010000110";
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-- IP
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-- IP
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pr_seq: process(clk, rst_s, blk_in)
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pr_seq: process(clk, rst_s, blk_in)
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begin
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begin
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if rst_s = '1' then
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if rst_s = '1' then
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