URL https://opencores.org/ocsvn/distributed_intelligence/distributed_intelligence/trunk

Subversion Repositories distributed_intelligence

[/] [distributed_intelligence/] [trunk/] [SRC/] [bus_register_x16.vhd] - Diff between revs 7 and 8

Rev 7	Rev 8
Line 36...	Line 36...
`dataOut : out STD_LOGIC_VECTOR (15 downto 0));`	`dataOut : out STD_LOGIC_VECTOR (15 downto 0));`
`end bus_register_x16;`	`end bus_register_x16;`

`architecture Behavioral of bus_register_x16 is`	`architecture Behavioral of bus_register_x16 is`
`signal data: std_logic_vector(15 downto 0);`	`signal data: std_logic_vector(15 downto 0);`

`component bus_access_x16`
`Port ( en : in STD_LOGIC;`
`dataRead : in STD_LOGIC_VECTOR (15 downto 0);`
`dataWrite : out STD_LOGIC_VECTOR (15 downto 0));`
`end component;`
`begin`	`begin`

`ba: bus_access_x16`	`tristate: process(we, data) is`
`port map( en => we,`	`begin`
`dataRead=>data,`	`if we = '1' then`
`dataWrite=>dataOut);`	`dataOut <= data;`
	`else`
	`dataOut <= (others=>'Z');`
	`end if;`
	`end process;`

`readData: process(clk) is`	`readData: process(clk) is`
`begin`	`begin`
`if clk'event and clk = '1' then`	`if clk'event and clk = '1' then`
`if re = '1' then`	`if re = '1' then`