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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Author: Eyal Hochberg ////
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//// eyal@provartec.com ////
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//// ////
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//// Downloaded from: http://www.opencores.org ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2010 Provartec LTD ////
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//// www.provartec.com ////
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//// info@provartec.com ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation.////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more////
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//// details. http://www.gnu.org/licenses/lgpl.html ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//---------------------------------------------------------
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//---------------------------------------------------------
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//-- File generated by RobustVerilog parser
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//-- File generated by RobustVerilog parser
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//-- Version: 1.0
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//-- Version: 1.0
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//-- Invoked Fri Mar 25 23:31:23 2011
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//-- Invoked Fri Mar 25 23:31:23 2011
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//--
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//--
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//-- Source file: dma_core_ahbm_rd.v
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//-- Source file: dma_core_ahbm_rd.v
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//---------------------------------------------------------
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//---------------------------------------------------------
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module dma_ahb32_core0_ahbm_rd(clk,reset,load_wr,load_wr_cycle,joint_stall,load_req_in_prog,rd_ch_num,rd_port_num,rd_cmd_port,rd_burst_start,rd_burst_addr,rd_burst_size,rd_cmd_pending,rd_line_cmd,rd_cmd_line,rd_cmd_num,ch_fifo_wr,ch_fifo_wdata,ch_fifo_wsize,ch_fifo_wr_num,rd_transfer,rd_transfer_size,rd_transfer_num,rd_slverr,rd_clr,rd_clr_last,rd_clr_load,rd_clr_line,rd_clr_line_num,rd_hold,ahb_rd_timeout,ahb_rd_timeout_num,HADDR,HBURST,HSIZE,HTRANS,HLAST,HRDATA,HREADY,HRESP,HOLD,SYNC);
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module dma_ahb32_core0_ahbm_rd(clk,reset,load_wr,load_wr_cycle,joint_stall,load_req_in_prog,rd_ch_num,rd_port_num,rd_cmd_port,rd_burst_start,rd_burst_addr,rd_burst_size,rd_cmd_pending,rd_line_cmd,rd_cmd_line,rd_cmd_num,ch_fifo_wr,ch_fifo_wdata,ch_fifo_wsize,ch_fifo_wr_num,rd_transfer,rd_transfer_size,rd_transfer_num,rd_slverr,rd_clr,rd_clr_last,rd_clr_load,rd_clr_line,rd_clr_line_num,rd_hold,ahb_rd_timeout,ahb_rd_timeout_num,HADDR,HBURST,HSIZE,HTRANS,HLAST,HRDATA,HREADY,HRESP,HOLD,SYNC);
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input clk;
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input clk;
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input reset;
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input reset;
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output load_wr;
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output load_wr;
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output [1:0] load_wr_cycle;
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output [1:0] load_wr_cycle;
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input joint_stall;
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input joint_stall;
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//command
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//command
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input load_req_in_prog;
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input load_req_in_prog;
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input [2:0] rd_ch_num;
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input [2:0] rd_ch_num;
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output rd_port_num;
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output rd_port_num;
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input rd_cmd_port;
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input rd_cmd_port;
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input rd_burst_start;
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input rd_burst_start;
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input [32-1:0] rd_burst_addr;
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input [32-1:0] rd_burst_addr;
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input [7-1:0] rd_burst_size;
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input [7-1:0] rd_burst_size;
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output rd_cmd_pending;
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output rd_cmd_pending;
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input rd_line_cmd;
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input rd_line_cmd;
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output rd_cmd_line;
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output rd_cmd_line;
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output [2:0] rd_cmd_num;
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output [2:0] rd_cmd_num;
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//data
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//data
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output ch_fifo_wr;
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output ch_fifo_wr;
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output [32-1:0] ch_fifo_wdata;
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output [32-1:0] ch_fifo_wdata;
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output [3-1:0] ch_fifo_wsize;
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output [3-1:0] ch_fifo_wsize;
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output [2:0] ch_fifo_wr_num;
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output [2:0] ch_fifo_wr_num;
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output rd_transfer;
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output rd_transfer;
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output [3-1:0] rd_transfer_size;
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output [3-1:0] rd_transfer_size;
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output [2:0] rd_transfer_num;
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output [2:0] rd_transfer_num;
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//resp
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//resp
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output rd_slverr;
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output rd_slverr;
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output rd_clr;
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output rd_clr;
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output rd_clr_last;
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output rd_clr_last;
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output rd_clr_load;
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output rd_clr_load;
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output rd_clr_line;
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output rd_clr_line;
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output [2:0] rd_clr_line_num;
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output [2:0] rd_clr_line_num;
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output rd_hold;
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output rd_hold;
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output ahb_rd_timeout;
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output ahb_rd_timeout;
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output [2:0] ahb_rd_timeout_num;
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output [2:0] ahb_rd_timeout_num;
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output [32-1:0] HADDR;
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output [32-1:0] HADDR;
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output [2:0] HBURST;
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output [2:0] HBURST;
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output [1:0] HSIZE;
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output [1:0] HSIZE;
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output [1:0] HTRANS;
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output [1:0] HTRANS;
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output HLAST;
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output HLAST;
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input [32-1:0] HRDATA;
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input [32-1:0] HRDATA;
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input HREADY;
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input HREADY;
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input HRESP;
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input HRESP;
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input HOLD;
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input HOLD;
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input SYNC;
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input SYNC;
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wire [32-1:0] HADDR_base;
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wire [32-1:0] HADDR_base;
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wire [2:0] HBURST_pre;
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wire [2:0] HBURST_pre;
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wire [1:0] HSIZE_pre;
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wire [1:0] HSIZE_pre;
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wire [1:0] HSIZE_data;
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wire [1:0] HSIZE_data;
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wire [32-1:0] HADDR;
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wire [32-1:0] HADDR;
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wire [2:0] HBURST;
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wire [2:0] HBURST;
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wire [1:0] HSIZE;
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wire [1:0] HSIZE;
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reg [1:0] HTRANS;
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reg [1:0] HTRANS;
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wire ch_fifo_wr_pre;
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wire ch_fifo_wr_pre;
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wire ch_fifo_wr_pre_d;
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wire ch_fifo_wr_pre_d;
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wire ch_fifo_wr;
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wire ch_fifo_wr;
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wire ch_fifo_wr_stall;
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wire ch_fifo_wr_stall;
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wire ch_fifo_wr_last;
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wire ch_fifo_wr_last;
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reg [32-1:0] ch_fifo_wdata;
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reg [32-1:0] ch_fifo_wdata;
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wire [3-1:0] ch_fifo_wsize_pre;
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wire [3-1:0] ch_fifo_wsize_pre;
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reg [3-1:0] ch_fifo_wsize;
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reg [3-1:0] ch_fifo_wsize;
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reg [2:0] ch_fifo_wr_num;
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reg [2:0] ch_fifo_wr_num;
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wire rd_slverr_pre;
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wire rd_slverr_pre;
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wire rd_slverr;
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wire rd_slverr;
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wire wr_data;
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wire wr_data;
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wire load_wr_pre;
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wire load_wr_pre;
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reg [1:0] load_wr_cycle;
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reg [1:0] load_wr_cycle;
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wire load_wr_last;
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wire load_wr_last;
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reg data_phase;
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reg data_phase;
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wire [7-1:2] strb_num;
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wire [7-1:2] strb_num;
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reg [4:0] cmd_counter;
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reg [4:0] cmd_counter;
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wire [4:0] cmd_num;
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wire [4:0] cmd_num;
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wire cmd_last;
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wire cmd_last;
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wire [3-1:0] data_width;
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wire [3-1:0] data_width;
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wire ahb_cmd;
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wire ahb_cmd;
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wire ahb_cmd_first;
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wire ahb_cmd_first;
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wire ahb_cmd_last;
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wire ahb_cmd_last;
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reg ahb_cmd_last_d;
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reg ahb_cmd_last_d;
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wire ahb_data_last;
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wire ahb_data_last;
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wire ahb_idle;
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wire ahb_idle;
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wire ahb_busy;
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wire ahb_busy;
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wire cmd_pop_stall;
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wire cmd_pop_stall;
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wire cmd_pop;
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wire cmd_pop;
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wire cmd_empty;
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wire cmd_empty;
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wire cmd_full;
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wire cmd_full;
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wire cmd_next;
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wire cmd_next;
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wire cmd_data_empty;
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wire cmd_data_empty;
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wire cmd_data_full;
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wire cmd_data_full;
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wire cmd_pending_pre;
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wire cmd_pending_pre;
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wire load_data_in_prog;
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wire load_data_in_prog;
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wire rd_port_num;
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wire rd_port_num;
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wire [2:0] rd_ch_num_out_cmd;
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wire [2:0] rd_ch_num_out_cmd;
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wire [2:0] rd_ch_num_out_data;
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wire [2:0] rd_ch_num_out_data;
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wire rd_line_out;
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wire rd_line_out;
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wire port_change;
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wire port_change;
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wire port_change_end;
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wire port_change_end;
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wire port_change_stall;
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wire port_change_stall;
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wire rd_clr_pre;
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wire rd_clr_pre;
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wire rd_clr;
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wire rd_clr;
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wire rd_clr_last_pre;
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wire rd_clr_last_pre;
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wire rd_clr_last;
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wire rd_clr_last;
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wire rd_clr_line_pre;
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wire rd_clr_line_pre;
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wire rd_clr_line;
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wire rd_clr_line;
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reg rd_clr_line_wait_reg;
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reg rd_clr_line_wait_reg;
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wire rd_clr_line_wait;
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wire rd_clr_line_wait;
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wire rd_clr_line_idle;
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wire rd_clr_line_idle;
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reg [2:0] rd_clr_line_num_reg;
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reg [2:0] rd_clr_line_num_reg;
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wire rd_cmd_line_pre;
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wire rd_cmd_line_pre;
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wire rd_cmd_line;
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wire rd_cmd_line;
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reg [2:0] rd_cmd_num_reg;
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reg [2:0] rd_cmd_num_reg;
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wire ahb_cmd_line;
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wire ahb_cmd_line;
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wire joint_stall_change_pre;
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wire joint_stall_change_pre;
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wire joint_stall_change;
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wire joint_stall_change;
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wire joint_stall_last_pre;
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wire joint_stall_last_pre;
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reg joint_stall_last;
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reg joint_stall_last;
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wire rd_burst_stall;
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wire rd_burst_stall;
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wire rd_burst_start_d;
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wire rd_burst_start_d;
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parameter TRANS_IDLE = 2'b00;
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parameter TRANS_IDLE = 2'b00;
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parameter TRANS_BUSY = 2'b01;
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parameter TRANS_BUSY = 2'b01;
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parameter TRANS_NONSEQ = 2'b10;
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parameter TRANS_NONSEQ = 2'b10;
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parameter TRANS_SEQ = 2'b11;
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parameter TRANS_SEQ = 2'b11;
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parameter BURST_SINGLE = 3'b000;
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parameter BURST_SINGLE = 3'b000;
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parameter BURST_INCR4 = 3'b011;
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parameter BURST_INCR4 = 3'b011;
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parameter BURST_INCR8 = 3'b101;
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parameter BURST_INCR8 = 3'b101;
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parameter BURST_INCR16 = 3'b111;
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parameter BURST_INCR16 = 3'b111;
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assign rd_hold = cmd_data_full | load_data_in_prog;
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assign rd_hold = cmd_data_full | load_data_in_prog;
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assign wr_data = data_phase & HREADY;
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assign wr_data = data_phase & HREADY;
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assign load_wr_pre = load_data_in_prog & wr_data;
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assign load_wr_pre = load_data_in_prog & wr_data;
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assign ch_fifo_wr_pre = (~load_data_in_prog) & wr_data;
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assign ch_fifo_wr_pre = (~load_data_in_prog) & wr_data;
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assign ch_fifo_wr_last = ch_fifo_wr_pre & ahb_cmd_last_d;
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assign ch_fifo_wr_last = ch_fifo_wr_pre & ahb_cmd_last_d;
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assign cmd_pending_pre = HTRANS[1] & (~HREADY);
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assign cmd_pending_pre = HTRANS[1] & (~HREADY);
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assign ahb_cmd = HTRANS[1] & HREADY & (~HOLD);
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assign ahb_cmd = HTRANS[1] & HREADY & (~HOLD);
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assign ahb_cmd_first = ahb_cmd & (HTRANS[1:0] == TRANS_NONSEQ);
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assign ahb_cmd_first = ahb_cmd & (HTRANS[1:0] == TRANS_NONSEQ);
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assign ahb_cmd_last = ahb_cmd & cmd_last;
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assign ahb_cmd_last = ahb_cmd & cmd_last;
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assign ahb_idle = HTRANS[1:0] == TRANS_IDLE;
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assign ahb_idle = HTRANS[1:0] == TRANS_IDLE;
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assign ahb_busy = HTRANS[1:0] == TRANS_BUSY;
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assign ahb_busy = HTRANS[1:0] == TRANS_BUSY;
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assign rd_transfer = ch_fifo_wr;
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assign rd_transfer = ch_fifo_wr;
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assign rd_transfer_size = ch_fifo_wsize;
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assign rd_transfer_size = ch_fifo_wsize;
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assign rd_transfer_num = ch_fifo_wr_num;
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assign rd_transfer_num = ch_fifo_wr_num;
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assign rd_slverr_pre = data_phase & HREADY & HRESP;
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assign rd_slverr_pre = data_phase & HREADY & HRESP;
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assign rd_clr_pre = ahb_data_last & (~load_data_in_prog);
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assign rd_clr_pre = ahb_data_last & (~load_data_in_prog);
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assign rd_clr_last_pre = ahb_data_last & load_data_in_prog;
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assign rd_clr_last_pre = ahb_data_last & load_data_in_prog;
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assign rd_clr_load = rd_clr_last;
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assign rd_clr_load = rd_clr_last;
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prgen_delay #(1) delay_rd_slverr (.clk(clk), .reset(reset), .din(rd_slverr_pre), .dout(rd_slverr));
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prgen_delay #(1) delay_rd_slverr (.clk(clk), .reset(reset), .din(rd_slverr_pre), .dout(rd_slverr));
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prgen_delay #(1) delay_load_wr (.clk(clk), .reset(reset), .din(load_wr_pre), .dout(load_wr));
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prgen_delay #(1) delay_load_wr (.clk(clk), .reset(reset), .din(load_wr_pre), .dout(load_wr));
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prgen_delay #(1) delay_rd_clr (.clk(clk), .reset(reset), .din(rd_clr_pre), .dout(rd_clr));
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prgen_delay #(1) delay_rd_clr (.clk(clk), .reset(reset), .din(rd_clr_pre), .dout(rd_clr));
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prgen_delay #(1) delay_rd_clr_last (.clk(clk), .reset(reset), .din(rd_clr_last_pre), .dout(rd_clr_last));
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prgen_delay #(1) delay_rd_clr_last (.clk(clk), .reset(reset), .din(rd_clr_last_pre), .dout(rd_clr_last));
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prgen_delay #(1) delay_cmd_pending (.clk(clk), .reset(reset), .din(cmd_pending_pre), .dout(rd_cmd_pending));
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prgen_delay #(1) delay_cmd_pending (.clk(clk), .reset(reset), .din(cmd_pending_pre), .dout(rd_cmd_pending));
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assign rd_clr_line_wait = 1'b0;
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assign rd_clr_line_wait = 1'b0;
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assign rd_clr_line_idle = 1'b0;
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assign rd_clr_line_idle = 1'b0;
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assign rd_cmd_line_pre = 1'b0;
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assign rd_cmd_line_pre = 1'b0;
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assign rd_clr_line_pre = 1'b0;
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assign rd_clr_line_pre = 1'b0;
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assign rd_cmd_line = 1'b0;
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assign rd_cmd_line = 1'b0;
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assign rd_cmd_num = 3'd0;
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assign rd_cmd_num = 3'd0;
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assign rd_clr_line = 1'b0;
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assign rd_clr_line = 1'b0;
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assign rd_clr_line_num = 3'd0;
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assign rd_clr_line_num = 3'd0;
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prgen_delay #(1) delay_fifo_wr (.clk(clk), .reset(reset), .din(ch_fifo_wr_pre), .dout(ch_fifo_wr_pre_d));
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prgen_delay #(1) delay_fifo_wr (.clk(clk), .reset(reset), .din(ch_fifo_wr_pre), .dout(ch_fifo_wr_pre_d));
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assign joint_stall_change_pre = joint_stall & ((rd_transfer_num != rd_ch_num_out_data) | (HOLD & HREADY));
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assign joint_stall_change_pre = joint_stall & ((rd_transfer_num != rd_ch_num_out_data) | (HOLD & HREADY));
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assign joint_stall_last_pre = joint_stall & ahb_data_last & ahb_idle;
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assign joint_stall_last_pre = joint_stall & ahb_data_last & ahb_idle;
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prgen_delay #(1) delay_joint_stall_change (.clk(clk), .reset(reset), .din(joint_stall_change_pre), .dout(joint_stall_change));
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prgen_delay #(1) delay_joint_stall_change (.clk(clk), .reset(reset), .din(joint_stall_change_pre), .dout(joint_stall_change));
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always @(posedge clk or posedge reset)
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always @(posedge clk or posedge reset)
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if (reset)
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if (reset)
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joint_stall_last <= #1 1'b0;
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joint_stall_last <= #1 1'b0;
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else if (joint_stall_last_pre)
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else if (joint_stall_last_pre)
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joint_stall_last <= #1 1'b1;
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joint_stall_last <= #1 1'b1;
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else if (!joint_stall)
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else if (!joint_stall)
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joint_stall_last <= #1 1'b0;
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joint_stall_last <= #1 1'b0;
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assign ch_fifo_wr_stall = (joint_stall_change & (~ahb_idle)) | joint_stall_last | ahb_busy;
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assign ch_fifo_wr_stall = (joint_stall_change & (~ahb_idle)) | joint_stall_last | ahb_busy;
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prgen_stall stall_fifo_wr (.clk(clk), .reset(reset), .din(ch_fifo_wr_pre_d), .stall(ch_fifo_wr_stall), .dout(ch_fifo_wr));
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prgen_stall stall_fifo_wr (.clk(clk), .reset(reset), .din(ch_fifo_wr_pre_d), .stall(ch_fifo_wr_stall), .dout(ch_fifo_wr));
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assign cmd_pop_stall = joint_stall | port_change;
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assign cmd_pop_stall = joint_stall | port_change;
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prgen_stall stall_cmd_pop (.clk(clk), .reset(reset), .din(ahb_cmd_last), .stall(cmd_pop_stall), .dout(cmd_pop));
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prgen_stall stall_cmd_pop (.clk(clk), .reset(reset), .din(ahb_cmd_last), .stall(cmd_pop_stall), .dout(cmd_pop));
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assign cmd_num =
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assign cmd_num =
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HBURST == BURST_INCR16 ? 5'd16 :
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HBURST == BURST_INCR16 ? 5'd16 :
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HBURST == BURST_INCR8 ? 5'd8 :
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HBURST == BURST_INCR8 ? 5'd8 :
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HBURST == BURST_INCR4 ? 5'd4 : 5'd1;
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HBURST == BURST_INCR4 ? 5'd4 : 5'd1;
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assign load_wr_last = load_wr_pre & ahb_cmd_last_d;
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assign load_wr_last = load_wr_pre & ahb_cmd_last_d;
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always @(posedge clk or posedge reset)
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always @(posedge clk or posedge reset)
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if (reset)
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if (reset)
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load_wr_cycle <= #1 2'b00;
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load_wr_cycle <= #1 2'b00;
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else if (load_wr)
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else if (load_wr)
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load_wr_cycle <= #1 load_wr_cycle + 1'b1;
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load_wr_cycle <= #1 load_wr_cycle + 1'b1;
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assign ahb_data_last = ch_fifo_wr_last | load_wr_last;
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assign ahb_data_last = ch_fifo_wr_last | load_wr_last;
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always @(posedge clk or posedge reset)
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always @(posedge clk or posedge reset)
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if (reset)
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if (reset)
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ahb_cmd_last_d <= #1 1'b0;
|
ahb_cmd_last_d <= #1 1'b0;
|
else if (ahb_cmd_last)
|
else if (ahb_cmd_last)
|
ahb_cmd_last_d <= #1 1'b1;
|
ahb_cmd_last_d <= #1 1'b1;
|
else if (ahb_data_last)
|
else if (ahb_data_last)
|
ahb_cmd_last_d <= #1 1'b0;
|
ahb_cmd_last_d <= #1 1'b0;
|
|
|
assign cmd_last = cmd_counter == (cmd_num - 1'b1);
|
assign cmd_last = cmd_counter == (cmd_num - 1'b1);
|
|
|
always @(posedge clk or posedge reset)
|
always @(posedge clk or posedge reset)
|
if (reset)
|
if (reset)
|
cmd_counter <= #1 5'd0;
|
cmd_counter <= #1 5'd0;
|
else if (ahb_cmd_last)
|
else if (ahb_cmd_last)
|
cmd_counter <= #1 5'd0;
|
cmd_counter <= #1 5'd0;
|
else if (ahb_cmd)
|
else if (ahb_cmd)
|
cmd_counter <= #1 cmd_counter + 1'b1;
|
cmd_counter <= #1 cmd_counter + 1'b1;
|
|
|
always @(posedge clk or posedge reset)
|
always @(posedge clk or posedge reset)
|
if (reset)
|
if (reset)
|
data_phase <= #1 1'b0;
|
data_phase <= #1 1'b0;
|
else if (ahb_cmd)
|
else if (ahb_cmd)
|
data_phase <= #1 1'b1;
|
data_phase <= #1 1'b1;
|
else if (ahb_data_last)
|
else if (ahb_data_last)
|
data_phase <= #1 1'b0;
|
data_phase <= #1 1'b0;
|
|
|
|
|
assign data_width =
|
assign data_width =
|
HSIZE == 2'b00 ? 'd1 :
|
HSIZE == 2'b00 ? 'd1 :
|
HSIZE == 2'b01 ? 'd2 :
|
HSIZE == 2'b01 ? 'd2 :
|
HSIZE == 2'b10 ? 'd4 : 'd8;
|
HSIZE == 2'b10 ? 'd4 : 'd8;
|
|
|
assign ch_fifo_wsize_pre =
|
assign ch_fifo_wsize_pre =
|
HSIZE_data == 2'b00 ? 'd1 :
|
HSIZE_data == 2'b00 ? 'd1 :
|
HSIZE_data == 2'b01 ? 'd2 :
|
HSIZE_data == 2'b01 ? 'd2 :
|
HSIZE_data == 2'b10 ? 'd4 : 'd8;
|
HSIZE_data == 2'b10 ? 'd4 : 'd8;
|
|
|
|
|
|
|
always @(posedge clk or posedge reset)
|
always @(posedge clk or posedge reset)
|
if (reset)
|
if (reset)
|
begin
|
begin
|
ch_fifo_wsize <= #1 2'b00;
|
ch_fifo_wsize <= #1 2'b00;
|
ch_fifo_wdata <= #1 {32{1'b0}};
|
ch_fifo_wdata <= #1 {32{1'b0}};
|
ch_fifo_wr_num <= #1 3'b000;
|
ch_fifo_wr_num <= #1 3'b000;
|
end
|
end
|
else if (wr_data)
|
else if (wr_data)
|
begin
|
begin
|
ch_fifo_wsize <= #1 ch_fifo_wsize_pre;
|
ch_fifo_wsize <= #1 ch_fifo_wsize_pre;
|
ch_fifo_wdata <= #1 HRDATA;
|
ch_fifo_wdata <= #1 HRDATA;
|
ch_fifo_wr_num <= #1 rd_ch_num_out_data;
|
ch_fifo_wr_num <= #1 rd_ch_num_out_data;
|
end
|
end
|
|
|
|
|
assign cmd_next = 2 > 1 ? cmd_full : 1'b0;
|
assign cmd_next = 2 > 1 ? cmd_full : 1'b0;
|
|
|
assign HLAST = cmd_last & (~cmd_empty);
|
assign HLAST = cmd_last & (~cmd_empty);
|
|
|
|
|
assign rd_burst_stall = (ahb_idle & cmd_empty & ahb_cmd_last_d & (~ahb_data_last)) | joint_stall;
|
assign rd_burst_stall = (ahb_idle & cmd_empty & ahb_cmd_last_d & (~ahb_data_last)) | joint_stall;
|
|
|
prgen_stall stall_burst_start (.clk(clk), .reset(reset), .din(rd_burst_start), .stall(rd_burst_stall), .dout(rd_burst_start_d));
|
prgen_stall stall_burst_start (.clk(clk), .reset(reset), .din(rd_burst_start), .stall(rd_burst_stall), .dout(rd_burst_start_d));
|
|
|
always @(posedge clk or posedge reset)
|
always @(posedge clk or posedge reset)
|
if (reset)
|
if (reset)
|
HTRANS <= #1 TRANS_IDLE;
|
HTRANS <= #1 TRANS_IDLE;
|
else if (port_change)
|
else if (port_change)
|
HTRANS <= #1 TRANS_IDLE;
|
HTRANS <= #1 TRANS_IDLE;
|
else if (ahb_idle & port_change_end & (~cmd_data_empty))
|
else if (ahb_idle & port_change_end & (~cmd_data_empty))
|
HTRANS <= #1 TRANS_NONSEQ;
|
HTRANS <= #1 TRANS_NONSEQ;
|
else if (rd_clr_line & ahb_idle & ((~cmd_empty) | rd_burst_start))
|
else if (rd_clr_line & ahb_idle & ((~cmd_empty) | rd_burst_start))
|
HTRANS <= #1 TRANS_NONSEQ;
|
HTRANS <= #1 TRANS_NONSEQ;
|
else if (((rd_line_out | rd_cmd_line_pre | joint_stall) & ahb_cmd_last) | rd_clr_line_idle)
|
else if (((rd_line_out | rd_cmd_line_pre | joint_stall) & ahb_cmd_last) | rd_clr_line_idle)
|
HTRANS <= #1 TRANS_IDLE;
|
HTRANS <= #1 TRANS_IDLE;
|
else if ((rd_burst_start_d & (ahb_idle | ahb_cmd_last)) | (cmd_next & cmd_pop))
|
else if ((rd_burst_start_d & (ahb_idle | ahb_cmd_last)) | (cmd_next & cmd_pop))
|
HTRANS <= #1 TRANS_NONSEQ;
|
HTRANS <= #1 TRANS_NONSEQ;
|
else if (ahb_cmd_last)
|
else if (ahb_cmd_last)
|
HTRANS <= #1 TRANS_IDLE;
|
HTRANS <= #1 TRANS_IDLE;
|
else if (ahb_cmd & joint_stall)
|
else if (ahb_cmd & joint_stall)
|
HTRANS <= #1 TRANS_BUSY;
|
HTRANS <= #1 TRANS_BUSY;
|
else if (ahb_cmd | (ahb_busy & (~joint_stall)))
|
else if (ahb_cmd | (ahb_busy & (~joint_stall)))
|
HTRANS <= #1 TRANS_SEQ;
|
HTRANS <= #1 TRANS_SEQ;
|
|
|
|
|
assign HADDR = HADDR_base | {cmd_counter, {2{1'b0}}};
|
assign HADDR = HADDR_base | {cmd_counter, {2{1'b0}}};
|
|
|
assign strb_num = rd_burst_size[7-1:2];
|
assign strb_num = rd_burst_size[7-1:2];
|
|
|
assign HBURST_pre =
|
assign HBURST_pre =
|
strb_num == 'd16 ? BURST_INCR16 :
|
strb_num == 'd16 ? BURST_INCR16 :
|
strb_num == 'd8 ? BURST_INCR8 :
|
strb_num == 'd8 ? BURST_INCR8 :
|
strb_num == 'd4 ? BURST_INCR4 : BURST_SINGLE;
|
strb_num == 'd4 ? BURST_INCR4 : BURST_SINGLE;
|
|
|
assign HSIZE_pre =
|
assign HSIZE_pre =
|
rd_burst_size == 'd1 ? 2'b00 :
|
rd_burst_size == 'd1 ? 2'b00 :
|
rd_burst_size == 'd2 ? 2'b01 :
|
rd_burst_size == 'd2 ? 2'b01 :
|
rd_burst_size == 'd4 ? 2'b10 : 2;
|
rd_burst_size == 'd4 ? 2'b10 : 2;
|
|
|
|
|
|
|
prgen_fifo #(32+3+2+1+3+1, 2)
|
prgen_fifo #(32+3+2+1+3+1, 2)
|
cmd_fifo(
|
cmd_fifo(
|
.clk(clk),
|
.clk(clk),
|
.reset(reset),
|
.reset(reset),
|
.push(rd_burst_start),
|
.push(rd_burst_start),
|
.pop(cmd_pop),
|
.pop(cmd_pop),
|
.din({rd_burst_addr,
|
.din({rd_burst_addr,
|
HBURST_pre,
|
HBURST_pre,
|
HSIZE_pre,
|
HSIZE_pre,
|
rd_cmd_port,
|
rd_cmd_port,
|
rd_ch_num,
|
rd_ch_num,
|
rd_line_cmd
|
rd_line_cmd
|
}),
|
}),
|
.dout({HADDR_base,
|
.dout({HADDR_base,
|
HBURST,
|
HBURST,
|
HSIZE,
|
HSIZE,
|
rd_port_num,
|
rd_port_num,
|
rd_ch_num_out_cmd,
|
rd_ch_num_out_cmd,
|
ahb_cmd_line
|
ahb_cmd_line
|
}),
|
}),
|
.empty(cmd_empty),
|
.empty(cmd_empty),
|
.full(cmd_full)
|
.full(cmd_full)
|
);
|
);
|
|
|
|
|
|
|
prgen_fifo #(3+2+1+1, 2)
|
prgen_fifo #(3+2+1+1, 2)
|
cmd_data_fifo(
|
cmd_data_fifo(
|
.clk(clk),
|
.clk(clk),
|
.reset(reset),
|
.reset(reset),
|
.push(rd_burst_start),
|
.push(rd_burst_start),
|
.pop(ahb_data_last),
|
.pop(ahb_data_last),
|
.din({rd_ch_num,
|
.din({rd_ch_num,
|
HSIZE_pre,
|
HSIZE_pre,
|
load_req_in_prog,
|
load_req_in_prog,
|
rd_line_cmd
|
rd_line_cmd
|
}),
|
}),
|
.dout({rd_ch_num_out_data,
|
.dout({rd_ch_num_out_data,
|
HSIZE_data,
|
HSIZE_data,
|
load_data_in_prog,
|
load_data_in_prog,
|
rd_line_out
|
rd_line_out
|
}),
|
}),
|
.empty(cmd_data_empty),
|
.empty(cmd_data_empty),
|
.full(cmd_data_full)
|
.full(cmd_data_full)
|
);
|
);
|
|
|
|
|
|
|
assign port_change = 1'b0;
|
assign port_change = 1'b0;
|
assign port_change_end = 1'b0;
|
assign port_change_end = 1'b0;
|
|
|
|
|
dma_ahb32_core0_ahbm_timeout dma_ahb32_core0_ahbm_timeout (
|
dma_ahb32_core0_ahbm_timeout dma_ahb32_core0_ahbm_timeout (
|
.clk(clk),
|
.clk(clk),
|
.reset(reset),
|
.reset(reset),
|
.HTRANS(HTRANS),
|
.HTRANS(HTRANS),
|
.HREADY(HREADY),
|
.HREADY(HREADY),
|
.ahb_timeout(ahb_rd_timeout)
|
.ahb_timeout(ahb_rd_timeout)
|
);
|
);
|
|
|
assign ahb_rd_timeout_num = rd_ch_num_out_cmd;
|
assign ahb_rd_timeout_num = rd_ch_num_out_cmd;
|
|
|
|
|
|
|
endmodule
|
endmodule
|
|
|
|
|
|
|
|
|
|
|
|
|