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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Author: Eyal Hochberg ////
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//// eyal@provartec.com ////
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//// ////
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//// Downloaded from: http://www.opencores.org ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2010 Provartec LTD ////
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//// www.provartec.com ////
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//// info@provartec.com ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation.////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more////
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//// details. http://www.gnu.org/licenses/lgpl.html ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//---------------------------------------------------------
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//---------------------------------------------------------
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//-- File generated by RobustVerilog parser
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//-- File generated by RobustVerilog parser
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//-- Version: 1.0
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//-- Version: 1.0
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//-- Invoked Fri Mar 25 23:31:22 2011
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//-- Invoked Fri Mar 25 23:31:22 2011
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//--
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//--
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//-- Source file: dma_core_top.v
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//-- Source file: dma_core_top.v
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//---------------------------------------------------------
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//---------------------------------------------------------
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module dma_ahb32_core0_top(clk,reset,scan_en,idle,ch_int_all_proc,ch_start,clkdiv,periph_tx_req,periph_tx_clr,periph_rx_req,periph_rx_clr,pclken,psel,penable,paddr,pwrite,pwdata,prdata,pslverr,pready,rd_port_num,wr_port_num,joint_mode,joint_remote,rd_prio_top,rd_prio_high,rd_prio_top_num,rd_prio_high_num,wr_prio_top,wr_prio_high,wr_prio_top_num,wr_prio_high_num,WHADDR,WHBURST,WHSIZE,WHTRANS,WHWDATA,WHREADY,WHRESP,RHADDR,RHBURST,RHSIZE,RHTRANS,RHRDATA,RHREADY,RHRESP,WHLAST,WHOLD,RHLAST,RHOLD);
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module dma_ahb32_core0_top(clk,reset,scan_en,idle,ch_int_all_proc,ch_start,clkdiv,periph_tx_req,periph_tx_clr,periph_rx_req,periph_rx_clr,pclken,psel,penable,paddr,pwrite,pwdata,prdata,pslverr,pready,rd_port_num,wr_port_num,joint_mode,joint_remote,rd_prio_top,rd_prio_high,rd_prio_top_num,rd_prio_high_num,wr_prio_top,wr_prio_high,wr_prio_top_num,wr_prio_high_num,WHADDR,WHBURST,WHSIZE,WHTRANS,WHWDATA,WHREADY,WHRESP,RHADDR,RHBURST,RHSIZE,RHTRANS,RHRDATA,RHREADY,RHRESP,WHLAST,WHOLD,RHLAST,RHOLD);
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input clk;
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input clk;
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input reset;
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input reset;
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input scan_en;
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input scan_en;
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output idle;
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output idle;
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output [8*1-1:0] ch_int_all_proc;
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output [8*1-1:0] ch_int_all_proc;
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input [7:0] ch_start;
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input [7:0] ch_start;
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input [3:0] clkdiv;
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input [3:0] clkdiv;
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input [31:1] periph_tx_req;
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input [31:1] periph_tx_req;
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output [31:1] periph_tx_clr;
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output [31:1] periph_tx_clr;
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input [31:1] periph_rx_req;
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input [31:1] periph_rx_req;
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output [31:1] periph_rx_clr;
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output [31:1] periph_rx_clr;
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input pclken;
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input pclken;
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input psel;
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input psel;
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input penable;
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input penable;
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input [10:0] paddr;
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input [10:0] paddr;
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input pwrite;
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input pwrite;
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input [31:0] pwdata;
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input [31:0] pwdata;
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output [31:0] prdata;
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output [31:0] prdata;
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output pslverr;
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output pslverr;
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output pready;
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output pready;
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output rd_port_num;
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output rd_port_num;
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output wr_port_num;
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output wr_port_num;
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input joint_mode;
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input joint_mode;
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input joint_remote;
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input joint_remote;
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input rd_prio_top;
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input rd_prio_top;
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input rd_prio_high;
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input rd_prio_high;
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input [2:0] rd_prio_top_num;
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input [2:0] rd_prio_top_num;
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input [2:0] rd_prio_high_num;
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input [2:0] rd_prio_high_num;
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input wr_prio_top;
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input wr_prio_top;
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input wr_prio_high;
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input wr_prio_high;
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input [2:0] wr_prio_top_num;
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input [2:0] wr_prio_top_num;
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input [2:0] wr_prio_high_num;
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input [2:0] wr_prio_high_num;
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output [32-1:0] WHADDR;
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output [32-1:0] WHADDR;
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output [2:0] WHBURST;
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output [2:0] WHBURST;
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output [1:0] WHSIZE;
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output [1:0] WHSIZE;
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output [1:0] WHTRANS;
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output [1:0] WHTRANS;
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output [32-1:0] WHWDATA;
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output [32-1:0] WHWDATA;
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input WHREADY;
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input WHREADY;
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input WHRESP;
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input WHRESP;
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output [32-1:0] RHADDR;
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output [32-1:0] RHADDR;
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output [2:0] RHBURST;
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output [2:0] RHBURST;
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output [1:0] RHSIZE;
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output [1:0] RHSIZE;
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output [1:0] RHTRANS;
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output [1:0] RHTRANS;
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input [32-1:0] RHRDATA;
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input [32-1:0] RHRDATA;
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input RHREADY;
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input RHREADY;
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input RHRESP;
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input RHRESP;
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output WHLAST;
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output WHLAST;
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input WHOLD;
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input WHOLD;
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output RHLAST;
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output RHLAST;
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input RHOLD;
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input RHOLD;
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wire [32-1:0] slow_WHADDR;
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wire [32-1:0] slow_WHADDR;
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wire [2:0] slow_WHBURST;
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wire [2:0] slow_WHBURST;
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wire [1:0] slow_WHSIZE;
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wire [1:0] slow_WHSIZE;
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wire [1:0] slow_WHTRANS;
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wire [1:0] slow_WHTRANS;
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wire [32-1:0] slow_WHWDATA;
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wire [32-1:0] slow_WHWDATA;
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wire slow_WHREADY;
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wire slow_WHREADY;
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wire slow_WHRESP;
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wire slow_WHRESP;
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wire [32-1:0] slow_RHADDR;
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wire [32-1:0] slow_RHADDR;
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wire [2:0] slow_RHBURST;
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wire [2:0] slow_RHBURST;
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wire [1:0] slow_RHSIZE;
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wire [1:0] slow_RHSIZE;
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wire [1:0] slow_RHTRANS;
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wire [1:0] slow_RHTRANS;
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wire [32-1:0] slow_RHRDATA;
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wire [32-1:0] slow_RHRDATA;
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wire slow_RHREADY;
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wire slow_RHREADY;
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wire slow_RHRESP;
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wire slow_RHRESP;
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wire slow_WHLAST;
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wire slow_WHLAST;
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wire slow_WHOLD;
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wire slow_WHOLD;
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wire slow_RHLAST;
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wire slow_RHLAST;
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wire slow_RHOLD;
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wire slow_RHOLD;
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wire slow_WSYNC;
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wire slow_WSYNC;
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wire slow_RSYNC;
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wire slow_RSYNC;
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wire slow_rd_port_num;
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wire slow_rd_port_num;
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wire slow_wr_port_num;
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wire slow_wr_port_num;
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wire clk_out;
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wire clk_out;
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wire clken;
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wire clken;
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wire bypass;
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wire bypass;
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assign clk_out = clk;
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assign clk_out = clk;
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assign clken = 1'b1;
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assign clken = 1'b1;
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assign WHADDR = slow_WHADDR;
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assign WHADDR = slow_WHADDR;
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assign WHBURST = slow_WHBURST;
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assign WHBURST = slow_WHBURST;
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assign WHSIZE = slow_WHSIZE;
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assign WHSIZE = slow_WHSIZE;
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assign WHTRANS = slow_WHTRANS;
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assign WHTRANS = slow_WHTRANS;
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assign WHWDATA = slow_WHWDATA;
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assign WHWDATA = slow_WHWDATA;
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assign RHADDR = slow_RHADDR;
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assign RHADDR = slow_RHADDR;
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assign RHBURST = slow_RHBURST;
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assign RHBURST = slow_RHBURST;
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assign RHSIZE = slow_RHSIZE;
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assign RHSIZE = slow_RHSIZE;
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assign RHTRANS = slow_RHTRANS;
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assign RHTRANS = slow_RHTRANS;
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assign WHLAST = slow_WHLAST;
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assign WHLAST = slow_WHLAST;
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assign RHLAST = slow_RHLAST;
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assign RHLAST = slow_RHLAST;
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assign slow_WHREADY = WHREADY;
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assign slow_WHREADY = WHREADY;
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assign slow_WHRESP = WHRESP;
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assign slow_WHRESP = WHRESP;
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assign slow_RHRDATA = RHRDATA;
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assign slow_RHRDATA = RHRDATA;
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assign slow_RHREADY = RHREADY;
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assign slow_RHREADY = RHREADY;
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assign slow_RHRESP = RHRESP;
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assign slow_RHRESP = RHRESP;
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assign slow_WHOLD = WHOLD;
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assign slow_WHOLD = WHOLD;
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assign slow_RHOLD = RHOLD;
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assign slow_RHOLD = RHOLD;
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assign slow_WSYNC = 1'b0;
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assign slow_WSYNC = 1'b0;
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assign slow_RSYNC = 1'b0;
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assign slow_RSYNC = 1'b0;
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assign rd_port_num = slow_rd_port_num;
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assign rd_port_num = slow_rd_port_num;
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assign wr_port_num = slow_wr_port_num;
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assign wr_port_num = slow_wr_port_num;
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dma_ahb32_core0
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dma_ahb32_core0
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dma_ahb32_core0 (
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dma_ahb32_core0 (
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.clk(clk_out),
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.clk(clk_out),
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.reset(reset),
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.reset(reset),
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.scan_en(scan_en),
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.scan_en(scan_en),
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.idle(idle),
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.idle(idle),
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.ch_int_all_proc(ch_int_all_proc),
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.ch_int_all_proc(ch_int_all_proc),
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.ch_start(ch_start),
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.ch_start(ch_start),
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.periph_tx_req(periph_tx_req),
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.periph_tx_req(periph_tx_req),
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.periph_tx_clr(periph_tx_clr),
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.periph_tx_clr(periph_tx_clr),
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.periph_rx_req(periph_rx_req),
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.periph_rx_req(periph_rx_req),
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.periph_rx_clr(periph_rx_clr),
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.periph_rx_clr(periph_rx_clr),
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.pclk(clk),
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.pclk(clk),
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.clken(clken),
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.clken(clken),
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.pclken(pclken),
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.pclken(pclken),
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.psel(psel),
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.psel(psel),
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.penable(penable),
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.penable(penable),
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.paddr(paddr[10:0]),
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.paddr(paddr[10:0]),
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.pwrite(pwrite),
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.pwrite(pwrite),
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.pwdata(pwdata),
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.pwdata(pwdata),
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.prdata(prdata),
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.prdata(prdata),
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.pslverr(pslverr),
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.pslverr(pslverr),
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.joint_mode_in(joint_mode),
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.joint_mode_in(joint_mode),
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.joint_remote(joint_remote),
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.joint_remote(joint_remote),
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.rd_prio_top(rd_prio_top),
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.rd_prio_top(rd_prio_top),
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.rd_prio_high(rd_prio_high),
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.rd_prio_high(rd_prio_high),
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.rd_prio_top_num(rd_prio_top_num),
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.rd_prio_top_num(rd_prio_top_num),
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.rd_prio_high_num(rd_prio_high_num),
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.rd_prio_high_num(rd_prio_high_num),
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.wr_prio_top(wr_prio_top),
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.wr_prio_top(wr_prio_top),
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.wr_prio_high(wr_prio_high),
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.wr_prio_high(wr_prio_high),
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.wr_prio_top_num(wr_prio_top_num),
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.wr_prio_top_num(wr_prio_top_num),
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.wr_prio_high_num(wr_prio_high_num),
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.wr_prio_high_num(wr_prio_high_num),
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.rd_port_num(slow_rd_port_num),
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.rd_port_num(slow_rd_port_num),
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.wr_port_num(slow_wr_port_num),
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.wr_port_num(slow_wr_port_num),
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.WHADDR(slow_WHADDR),
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.WHADDR(slow_WHADDR),
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.WHBURST(slow_WHBURST),
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.WHBURST(slow_WHBURST),
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.WHSIZE(slow_WHSIZE),
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.WHSIZE(slow_WHSIZE),
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.WHTRANS(slow_WHTRANS),
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.WHTRANS(slow_WHTRANS),
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.WHWDATA(slow_WHWDATA),
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.WHWDATA(slow_WHWDATA),
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.WHREADY(slow_WHREADY),
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.WHREADY(slow_WHREADY),
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.WHRESP(slow_WHRESP),
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.WHRESP(slow_WHRESP),
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.RHADDR(slow_RHADDR),
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.RHADDR(slow_RHADDR),
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.RHBURST(slow_RHBURST),
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.RHBURST(slow_RHBURST),
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.RHSIZE(slow_RHSIZE),
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.RHSIZE(slow_RHSIZE),
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.RHTRANS(slow_RHTRANS),
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.RHTRANS(slow_RHTRANS),
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.RHRDATA(slow_RHRDATA),
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.RHRDATA(slow_RHRDATA),
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.RHREADY(slow_RHREADY),
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.RHREADY(slow_RHREADY),
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.RHRESP(slow_RHRESP),
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.RHRESP(slow_RHRESP),
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.WHLAST(slow_WHLAST),
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.WHLAST(slow_WHLAST),
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.WHOLD(slow_WHOLD),
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.WHOLD(slow_WHOLD),
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.RHLAST(slow_RHLAST),
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.RHLAST(slow_RHLAST),
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.RHOLD(slow_RHOLD),
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.RHOLD(slow_RHOLD),
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.WSYNC(slow_WSYNC),
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.WSYNC(slow_WSYNC),
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.RSYNC(slow_RSYNC)
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.RSYNC(slow_RSYNC)
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);
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);
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endmodule
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endmodule
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