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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Author: Eyal Hochberg ////
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//// eyal@provartec.com ////
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//// ////
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//// Downloaded from: http://www.opencores.org ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2010 Provartec LTD ////
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//// www.provartec.com ////
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//// info@provartec.com ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation.////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more////
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//// details. http://www.gnu.org/licenses/lgpl.html ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//---------------------------------------------------------
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//---------------------------------------------------------
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//-- File generated by RobustVerilog parser
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//-- File generated by RobustVerilog parser
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//-- Version: 1.0
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//-- Version: 1.0
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//-- Invoked Fri Mar 25 23:32:59 2011
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//-- Invoked Fri Mar 25 23:32:59 2011
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//--
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//--
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//-- Source file: dma_core_ahbm_wr.v
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//-- Source file: dma_core_ahbm_wr.v
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//---------------------------------------------------------
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//---------------------------------------------------------
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module dma_ahb64_core0_ahbm_wr(clk,reset,rd_transfer,rd_transfer_size,joint_req,joint_in_prog,joint_stall,wr_last_cmd,wr_ch_num,wr_ch_num_resp,wr_port_num,wr_cmd_port,wr_burst_start,wr_burst_addr,wr_burst_size,wr_cmd_pending,wr_line_cmd,ch_fifo_rd,ch_fifo_rd_num,ch_fifo_rdata,ch_fifo_rd_valid,ch_fifo_rsize,ch_fifo_wr_ready,wr_transfer,wr_transfer_num,wr_transfer_size,wr_next_size,wr_slverr,wr_clr,wr_clr_last,wr_clr_line,wr_clr_line_num,wr_cmd_full,wr_hold,ahb_wr_timeout,ahb_wr_timeout_num,HADDR,HBURST,HSIZE,HTRANS,HLAST,HWDATA,HREADY,HRESP,HOLD,SYNC);
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module dma_ahb64_core0_ahbm_wr(clk,reset,rd_transfer,rd_transfer_size,joint_req,joint_in_prog,joint_stall,wr_last_cmd,wr_ch_num,wr_ch_num_resp,wr_port_num,wr_cmd_port,wr_burst_start,wr_burst_addr,wr_burst_size,wr_cmd_pending,wr_line_cmd,ch_fifo_rd,ch_fifo_rd_num,ch_fifo_rdata,ch_fifo_rd_valid,ch_fifo_rsize,ch_fifo_wr_ready,wr_transfer,wr_transfer_num,wr_transfer_size,wr_next_size,wr_slverr,wr_clr,wr_clr_last,wr_clr_line,wr_clr_line_num,wr_cmd_full,wr_hold,ahb_wr_timeout,ahb_wr_timeout_num,HADDR,HBURST,HSIZE,HTRANS,HLAST,HWDATA,HREADY,HRESP,HOLD,SYNC);
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input clk;
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input clk;
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input reset;
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input reset;
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input rd_transfer;
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input rd_transfer;
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input [4-1:0] rd_transfer_size;
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input [4-1:0] rd_transfer_size;
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input joint_req;
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input joint_req;
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input joint_in_prog;
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input joint_in_prog;
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output joint_stall;
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output joint_stall;
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//command
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//command
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input wr_last_cmd;
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input wr_last_cmd;
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input [2:0] wr_ch_num;
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input [2:0] wr_ch_num;
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output [2:0] wr_ch_num_resp;
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output [2:0] wr_ch_num_resp;
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output wr_port_num;
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output wr_port_num;
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input wr_cmd_port;
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input wr_cmd_port;
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input wr_burst_start;
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input wr_burst_start;
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input [32-1:0] wr_burst_addr;
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input [32-1:0] wr_burst_addr;
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input [8-1:0] wr_burst_size;
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input [8-1:0] wr_burst_size;
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output wr_cmd_pending;
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output wr_cmd_pending;
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input wr_line_cmd;
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input wr_line_cmd;
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//data
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//data
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output ch_fifo_rd;
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output ch_fifo_rd;
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output [2:0] ch_fifo_rd_num;
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output [2:0] ch_fifo_rd_num;
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input [64-1:0] ch_fifo_rdata;
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input [64-1:0] ch_fifo_rdata;
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input ch_fifo_rd_valid;
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input ch_fifo_rd_valid;
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output [4-1:0] ch_fifo_rsize;
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output [4-1:0] ch_fifo_rsize;
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input ch_fifo_wr_ready;
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input ch_fifo_wr_ready;
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output wr_transfer;
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output wr_transfer;
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output [2:0] wr_transfer_num;
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output [2:0] wr_transfer_num;
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output [4-1:0] wr_transfer_size;
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output [4-1:0] wr_transfer_size;
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output [4-1:0] wr_next_size;
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output [4-1:0] wr_next_size;
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//resp
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//resp
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output wr_slverr;
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output wr_slverr;
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output wr_clr;
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output wr_clr;
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output wr_clr_last;
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output wr_clr_last;
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output wr_clr_line;
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output wr_clr_line;
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output [2:0] wr_clr_line_num;
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output [2:0] wr_clr_line_num;
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output wr_cmd_full;
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output wr_cmd_full;
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output wr_hold;
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output wr_hold;
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output ahb_wr_timeout;
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output ahb_wr_timeout;
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output [2:0] ahb_wr_timeout_num;
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output [2:0] ahb_wr_timeout_num;
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output [32-1:0] HADDR;
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output [32-1:0] HADDR;
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output [2:0] HBURST;
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output [2:0] HBURST;
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output [1:0] HSIZE;
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output [1:0] HSIZE;
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output [1:0] HTRANS;
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output [1:0] HTRANS;
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output HLAST;
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output HLAST;
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output [64-1:0] HWDATA;
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output [64-1:0] HWDATA;
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input HREADY;
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input HREADY;
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input HRESP;
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input HRESP;
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input HOLD;
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input HOLD;
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input SYNC;
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input SYNC;
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wire [32-1:0] HADDR_base;
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wire [32-1:0] HADDR_base;
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wire [2:0] HBURST_pre;
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wire [2:0] HBURST_pre;
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wire [1:0] HSIZE_pre;
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wire [1:0] HSIZE_pre;
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wire [2:0] HBURST;
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wire [2:0] HBURST;
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wire [1:0] HSIZE;
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wire [1:0] HSIZE;
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reg [1:0] HTRANS;
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reg [1:0] HTRANS;
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wire [64-1:0] HWDATA;
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wire [64-1:0] HWDATA;
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wire wr_last_cmd_out;
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wire wr_last_cmd_out;
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wire ch_fifo_rd_last;
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wire ch_fifo_rd_last;
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wire data_ready_pre;
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wire data_ready_pre;
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wire data_ready;
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wire data_ready;
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reg data_phase;
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reg data_phase;
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reg [3:0] data_counter;
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reg [3:0] data_counter;
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wire [3:0] data_num_pre;
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wire [3:0] data_num_pre;
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wire [3:0] data_num;
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wire [3:0] data_num;
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wire data_last;
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wire data_last;
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wire data_pending_pre;
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wire data_pending_pre;
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wire data_pending;
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wire data_pending;
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wire [8-1:3] strb_num;
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wire [8-1:3] strb_num;
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reg [3:0] cmd_counter;
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reg [3:0] cmd_counter;
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reg [3:0] last_counter;
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reg [3:0] last_counter;
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wire [3:0] cmd_num;
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wire [3:0] cmd_num;
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wire cmd_single_in;
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wire cmd_single_in;
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wire cmd_single_out;
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wire cmd_single_out;
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wire cmd_last;
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wire cmd_last;
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wire cmd_empty;
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wire cmd_empty;
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wire cmd_full;
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wire cmd_full;
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wire cmd_data_empty;
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wire cmd_data_empty;
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wire cmd_data_full;
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wire cmd_data_full;
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wire data_empty;
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wire data_empty;
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wire data_full;
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wire data_full;
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wire [2:0] data_fullness_pre;
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wire [2:0] data_fullness_pre;
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reg [2:0] data_fullness;
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reg [2:0] data_fullness;
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reg [1:0] data_on_the_way;
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reg [1:0] data_on_the_way;
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wire [4-1:0] data_width;
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wire [4-1:0] data_width;
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wire ahb_cmd;
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wire ahb_cmd;
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wire ahb_cmd_first;
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wire ahb_cmd_first;
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wire ahb_cmd_last;
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wire ahb_cmd_last;
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wire ahb_data_last;
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wire ahb_data_last;
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wire ahb_idle;
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wire ahb_idle;
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wire ahb_busy;
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wire ahb_busy;
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wire [4-1:0] wr_next_size_in;
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wire [4-1:0] wr_next_size_in;
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wire wr_transfer_pre;
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wire wr_transfer_pre;
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reg [4-1:0] wr_transfer_size_pre;
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reg [4-1:0] wr_transfer_size_pre;
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reg [2:0] wr_transfer_num_pre;
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reg [2:0] wr_transfer_num_pre;
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wire wr_transfer;
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wire wr_transfer;
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reg [4-1:0] wr_transfer_size;
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reg [4-1:0] wr_transfer_size;
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reg [2:0] wr_transfer_num;
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reg [2:0] wr_transfer_num;
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reg [2:0] wr_ch_num_resp;
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reg [2:0] wr_ch_num_resp;
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wire wr_port_num;
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wire wr_port_num;
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wire [2:0] wr_ch_num_out;
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wire [2:0] wr_ch_num_out;
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wire [2:0] ch_fifo_rd_num;
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wire [2:0] ch_fifo_rd_num;
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wire wr_clr_pre;
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wire wr_clr_pre;
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wire wr_clr;
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wire wr_clr;
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wire wr_clr_last_pre;
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wire wr_clr_last_pre;
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wire wr_clr_last;
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wire wr_clr_last;
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wire wr_clr_line_pre;
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wire wr_clr_line_pre;
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wire wr_clr_line_pre_d;
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wire wr_clr_line_pre_d;
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wire wr_clr_line_stall;
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wire wr_clr_line_stall;
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wire wr_clr_line;
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wire wr_clr_line;
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wire wr_line_out;
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wire wr_line_out;
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wire port_change;
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wire port_change;
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wire port_change_end;
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wire port_change_end;
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reg [2:0] wr_clr_line_num_reg;
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reg [2:0] wr_clr_line_num_reg;
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reg ahb_cmd_last_d;
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reg ahb_cmd_last_d;
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reg wr_last_cmd_d;
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reg wr_last_cmd_d;
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wire wr_last_cmd_valid;
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wire wr_last_cmd_valid;
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wire cmd_pending_pre;
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wire cmd_pending_pre;
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wire wr_slverr_pre;
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wire wr_slverr_pre;
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reg wr_slverr_reg;
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reg wr_slverr_reg;
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wire joint_req_out;
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wire joint_req_out;
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wire [4-1:0] rd_transfer_size_joint;
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wire [4-1:0] rd_transfer_size_joint;
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wire rd_transfer_full;
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wire rd_transfer_full;
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wire joint_stall;
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wire joint_stall;
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wire joint_fifo_rd_valid;
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wire joint_fifo_rd_valid;
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parameter TRANS_IDLE = 2'b00;
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parameter TRANS_IDLE = 2'b00;
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parameter TRANS_BUSY = 2'b01;
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parameter TRANS_BUSY = 2'b01;
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parameter TRANS_NONSEQ = 2'b10;
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parameter TRANS_NONSEQ = 2'b10;
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parameter TRANS_SEQ = 2'b11;
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parameter TRANS_SEQ = 2'b11;
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parameter BURST_SINGLE = 3'b000;
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parameter BURST_SINGLE = 3'b000;
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parameter BURST_INCR4 = 3'b011;
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parameter BURST_INCR4 = 3'b011;
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parameter BURST_INCR8 = 3'b101;
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parameter BURST_INCR8 = 3'b101;
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parameter BURST_INCR16 = 3'b111;
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parameter BURST_INCR16 = 3'b111;
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prgen_joint_stall #(4)
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prgen_joint_stall #(4)
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gen_joint_stall (
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gen_joint_stall (
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.clk(clk),
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.clk(clk),
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.reset(reset),
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.reset(reset),
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.joint_req_out(joint_req_out),
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.joint_req_out(joint_req_out),
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.rd_transfer(rd_transfer),
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.rd_transfer(rd_transfer),
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.rd_transfer_size(rd_transfer_size),
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.rd_transfer_size(rd_transfer_size),
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.ch_fifo_rd(ch_fifo_rd),
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.ch_fifo_rd(ch_fifo_rd),
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.data_fullness_pre(data_fullness_pre),
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.data_fullness_pre(data_fullness_pre),
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.HOLD(HOLD),
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.HOLD(HOLD),
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.joint_fifo_rd_valid(joint_fifo_rd_valid),
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.joint_fifo_rd_valid(joint_fifo_rd_valid),
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.rd_transfer_size_joint(rd_transfer_size_joint),
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.rd_transfer_size_joint(rd_transfer_size_joint),
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.rd_transfer_full(rd_transfer_full),
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.rd_transfer_full(rd_transfer_full),
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.joint_stall(joint_stall)
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.joint_stall(joint_stall)
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);
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);
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prgen_delay #(2) delay_fifo_rd0 (.clk(clk), .reset(reset), .din(ch_fifo_rd), .dout(data_ready_pre));
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prgen_delay #(2) delay_fifo_rd0 (.clk(clk), .reset(reset), .din(ch_fifo_rd), .dout(data_ready_pre));
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prgen_delay #(1) delay_fifo_rd1 (.clk(clk), .reset(reset), .din(data_ready_pre), .dout(data_ready));
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prgen_delay #(1) delay_fifo_rd1 (.clk(clk), .reset(reset), .din(data_ready_pre), .dout(data_ready));
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assign ch_fifo_rd =
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assign ch_fifo_rd =
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joint_fifo_rd_valid |
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joint_fifo_rd_valid |
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((~cmd_data_empty) &
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((~cmd_data_empty) &
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(~data_pending) &
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(~data_pending) &
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(~wr_clr_line_stall) &
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(~wr_clr_line_stall) &
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(~joint_in_prog) &
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(~joint_in_prog) &
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& ch_fifo_wr_ready);
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& ch_fifo_wr_ready);
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assign wr_hold = cmd_full;
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assign wr_hold = cmd_full;
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assign ch_fifo_rd_last = ch_fifo_rd & data_last;
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assign ch_fifo_rd_last = ch_fifo_rd & data_last;
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assign cmd_pending_pre = HTRANS[1] & (~HREADY);
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assign cmd_pending_pre = HTRANS[1] & (~HREADY);
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assign ahb_cmd = HTRANS[1] & HREADY & (~HOLD);
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assign ahb_cmd = HTRANS[1] & HREADY & (~HOLD);
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assign ahb_cmd_first = ahb_cmd & (HTRANS[1:0] == TRANS_NONSEQ);
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assign ahb_cmd_first = ahb_cmd & (HTRANS[1:0] == TRANS_NONSEQ);
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assign ahb_cmd_last = ahb_cmd & cmd_last;
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assign ahb_cmd_last = ahb_cmd & cmd_last;
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assign ahb_idle = HTRANS[1:0] == TRANS_IDLE;
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assign ahb_idle = HTRANS[1:0] == TRANS_IDLE;
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assign ahb_busy = HTRANS[1:0] == TRANS_BUSY;
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assign ahb_busy = HTRANS[1:0] == TRANS_BUSY;
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assign wr_transfer_pre = data_phase & HREADY;
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assign wr_transfer_pre = data_phase & HREADY;
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assign wr_slverr_pre = data_phase & HREADY & HRESP;
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assign wr_slverr_pre = data_phase & HREADY & HRESP;
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assign wr_clr_line_pre = ch_fifo_rd_last & wr_line_out;
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assign wr_clr_line_pre = ch_fifo_rd_last & wr_line_out;
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assign wr_cmd_full = cmd_data_full | cmd_full;
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assign wr_cmd_full = cmd_data_full | cmd_full;
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prgen_stall stall_wr_clr (.clk(clk), .reset(reset), .din(ahb_data_last), .stall(SYNC), .dout(wr_clr_pre));
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prgen_stall stall_wr_clr (.clk(clk), .reset(reset), .din(ahb_data_last), .stall(SYNC), .dout(wr_clr_pre));
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prgen_stall stall_wr_clr_last (.clk(clk), .reset(reset), .din(wr_last_cmd_valid), .stall(SYNC), .dout(wr_clr_last_pre));
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prgen_stall stall_wr_clr_last (.clk(clk), .reset(reset), .din(wr_last_cmd_valid), .stall(SYNC), .dout(wr_clr_last_pre));
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prgen_delay #(1) delay_wr_clr (.clk(clk), .reset(reset), .din(wr_clr_pre), .dout(wr_clr));
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prgen_delay #(1) delay_wr_clr (.clk(clk), .reset(reset), .din(wr_clr_pre), .dout(wr_clr));
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prgen_delay #(1) delay_wr_clr_last (.clk(clk), .reset(reset), .din(wr_clr_last_pre), .dout(wr_clr_last));
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prgen_delay #(1) delay_wr_clr_last (.clk(clk), .reset(reset), .din(wr_clr_last_pre), .dout(wr_clr_last));
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prgen_delay #(1) delay_cmd_pending (.clk(clk), .reset(reset), .din(cmd_pending_pre), .dout(wr_cmd_pending));
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prgen_delay #(1) delay_cmd_pending (.clk(clk), .reset(reset), .din(cmd_pending_pre), .dout(wr_cmd_pending));
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always @(posedge clk or posedge reset)
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always @(posedge clk or posedge reset)
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if (reset)
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if (reset)
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ahb_cmd_last_d <= #1 1'b0;
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ahb_cmd_last_d <= #1 1'b0;
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else if (ahb_cmd_last)
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else if (ahb_cmd_last)
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ahb_cmd_last_d <= #1 1'b1;
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ahb_cmd_last_d <= #1 1'b1;
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else if (ahb_data_last)
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else if (ahb_data_last)
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ahb_cmd_last_d <= #1 1'b0;
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ahb_cmd_last_d <= #1 1'b0;
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always @(posedge clk or posedge reset)
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always @(posedge clk or posedge reset)
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if (reset)
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if (reset)
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wr_last_cmd_d <= #1 1'b0;
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wr_last_cmd_d <= #1 1'b0;
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else if (ahb_cmd_last)
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else if (ahb_cmd_last)
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wr_last_cmd_d <= #1 wr_last_cmd_out;
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wr_last_cmd_d <= #1 wr_last_cmd_out;
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else if (ahb_data_last)
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else if (ahb_data_last)
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wr_last_cmd_d <= #1 1'b0;
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wr_last_cmd_d <= #1 1'b0;
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always @(posedge clk or posedge reset)
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always @(posedge clk or posedge reset)
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if (reset)
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if (reset)
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wr_slverr_reg <= #1 1'b0;
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wr_slverr_reg <= #1 1'b0;
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else if (wr_slverr_pre)
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else if (wr_slverr_pre)
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wr_slverr_reg <= #1 1'b1;
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wr_slverr_reg <= #1 1'b1;
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else if (wr_slverr)
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else if (wr_slverr)
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wr_slverr_reg <= #1 1'b0;
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wr_slverr_reg <= #1 1'b0;
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assign wr_slverr = wr_slverr_reg & wr_clr;
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assign wr_slverr = wr_slverr_reg & wr_clr;
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assign ahb_data_last = ahb_cmd_last_d & HREADY;
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assign ahb_data_last = ahb_cmd_last_d & HREADY;
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assign wr_last_cmd_valid = wr_last_cmd_d & ahb_data_last;
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assign wr_last_cmd_valid = wr_last_cmd_d & ahb_data_last;
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assign wr_clr_line = 1'b0;
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assign wr_clr_line = 1'b0;
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assign wr_clr_line_stall = 1'b0;
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assign wr_clr_line_stall = 1'b0;
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assign wr_clr_line_num = 3'd0;
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assign wr_clr_line_num = 3'd0;
|
|
|
|
|
|
|
assign cmd_num =
|
assign cmd_num =
|
HBURST == BURST_INCR16 ? 4'd15 :
|
HBURST == BURST_INCR16 ? 4'd15 :
|
HBURST == BURST_INCR8 ? 4'd7 :
|
HBURST == BURST_INCR8 ? 4'd7 :
|
HBURST == BURST_INCR4 ? 4'd3 : 4'd0;
|
HBURST == BURST_INCR4 ? 4'd3 : 4'd0;
|
|
|
assign cmd_last = cmd_single_out | (last_counter == 'd0);
|
assign cmd_last = cmd_single_out | (last_counter == 'd0);
|
|
|
always @(posedge clk or posedge reset)
|
always @(posedge clk or posedge reset)
|
if (reset)
|
if (reset)
|
last_counter <= #1 4'hf;
|
last_counter <= #1 4'hf;
|
else if (ahb_cmd & (HTRANS == TRANS_NONSEQ))
|
else if (ahb_cmd & (HTRANS == TRANS_NONSEQ))
|
last_counter <= #1 cmd_num - 1'b1;
|
last_counter <= #1 cmd_num - 1'b1;
|
else if (ahb_cmd)
|
else if (ahb_cmd)
|
last_counter <= #1 last_counter - 1'b1;
|
last_counter <= #1 last_counter - 1'b1;
|
|
|
always @(posedge clk or posedge reset)
|
always @(posedge clk or posedge reset)
|
if (reset)
|
if (reset)
|
cmd_counter <= #1 4'd0;
|
cmd_counter <= #1 4'd0;
|
else if (ahb_cmd_last)
|
else if (ahb_cmd_last)
|
cmd_counter <= #1 4'd0;
|
cmd_counter <= #1 4'd0;
|
else if (ahb_cmd)
|
else if (ahb_cmd)
|
cmd_counter <= #1 cmd_counter + 1'b1;
|
cmd_counter <= #1 cmd_counter + 1'b1;
|
|
|
assign data_last = data_counter == data_num;
|
assign data_last = data_counter == data_num;
|
|
|
always @(posedge clk or posedge reset)
|
always @(posedge clk or posedge reset)
|
if (reset)
|
if (reset)
|
data_counter <= #1 4'd0;
|
data_counter <= #1 4'd0;
|
else if (ch_fifo_rd & data_last)
|
else if (ch_fifo_rd & data_last)
|
data_counter <= #1 4'd0;
|
data_counter <= #1 4'd0;
|
else if (ch_fifo_rd)
|
else if (ch_fifo_rd)
|
data_counter <= #1 data_counter + 1'b1;
|
data_counter <= #1 data_counter + 1'b1;
|
|
|
always @(posedge clk or posedge reset)
|
always @(posedge clk or posedge reset)
|
if (reset)
|
if (reset)
|
data_phase <= #1 1'b0;
|
data_phase <= #1 1'b0;
|
else if (ahb_cmd)
|
else if (ahb_cmd)
|
data_phase <= #1 1'b1;
|
data_phase <= #1 1'b1;
|
else if (ahb_data_last)
|
else if (ahb_data_last)
|
data_phase <= #1 1'b0;
|
data_phase <= #1 1'b0;
|
|
|
|
|
assign data_width =
|
assign data_width =
|
HSIZE == 2'b00 ? 'd1 :
|
HSIZE == 2'b00 ? 'd1 :
|
HSIZE == 2'b01 ? 'd2 :
|
HSIZE == 2'b01 ? 'd2 :
|
HSIZE == 2'b10 ? 'd4 : 'd8;
|
HSIZE == 2'b10 ? 'd4 : 'd8;
|
|
|
assign wr_next_size_in = {|wr_burst_size[8-1:3], wr_burst_size[3-1:0]};
|
assign wr_next_size_in = {|wr_burst_size[8-1:3], wr_burst_size[3-1:0]};
|
|
|
assign ch_fifo_rsize = joint_fifo_rd_valid ? rd_transfer_size_joint : wr_next_size;
|
assign ch_fifo_rsize = joint_fifo_rd_valid ? rd_transfer_size_joint : wr_next_size;
|
|
|
assign HADDR = HADDR_base | {cmd_counter, {3{1'b0}}};
|
assign HADDR = HADDR_base | {cmd_counter, {3{1'b0}}};
|
|
|
assign strb_num = wr_burst_size[8-1:3];
|
assign strb_num = wr_burst_size[8-1:3];
|
|
|
assign cmd_single_in = strb_num <= 'd1;
|
assign cmd_single_in = strb_num <= 'd1;
|
|
|
assign data_num_pre =
|
assign data_num_pre =
|
strb_num == 'd16 ? 'd15 :
|
strb_num == 'd16 ? 'd15 :
|
strb_num == 'd8 ? 'd7 :
|
strb_num == 'd8 ? 'd7 :
|
strb_num == 'd4 ? 'd3 : 'd0;
|
strb_num == 'd4 ? 'd3 : 'd0;
|
|
|
assign HBURST_pre =
|
assign HBURST_pre =
|
strb_num == 'd16 ? BURST_INCR16 :
|
strb_num == 'd16 ? BURST_INCR16 :
|
strb_num == 'd8 ? BURST_INCR8 :
|
strb_num == 'd8 ? BURST_INCR8 :
|
strb_num == 'd4 ? BURST_INCR4 : BURST_SINGLE;
|
strb_num == 'd4 ? BURST_INCR4 : BURST_SINGLE;
|
|
|
assign HSIZE_pre =
|
assign HSIZE_pre =
|
wr_burst_size == 'd1 ? 2'b00 :
|
wr_burst_size == 'd1 ? 2'b00 :
|
wr_burst_size == 'd2 ? 2'b01 :
|
wr_burst_size == 'd2 ? 2'b01 :
|
wr_burst_size == 'd4 ? 2'b10 : 3;
|
wr_burst_size == 'd4 ? 2'b10 : 3;
|
|
|
assign HLAST = cmd_last & (~cmd_empty);
|
assign HLAST = cmd_last & (~cmd_empty);
|
|
|
always @(posedge clk or posedge reset)
|
always @(posedge clk or posedge reset)
|
if (reset)
|
if (reset)
|
HTRANS <= #1 TRANS_IDLE;
|
HTRANS <= #1 TRANS_IDLE;
|
else if (port_change)
|
else if (port_change)
|
HTRANS <= #1 TRANS_IDLE;
|
HTRANS <= #1 TRANS_IDLE;
|
else if (ahb_idle & port_change_end & (data_fullness_pre > 'd0))
|
else if (ahb_idle & port_change_end & (data_fullness_pre > 'd0))
|
HTRANS <= #1 TRANS_NONSEQ;
|
HTRANS <= #1 TRANS_NONSEQ;
|
else if (ahb_cmd_last & ((data_fullness > 'd2) | data_ready_pre)) //burst end and data ready
|
else if (ahb_cmd_last & ((data_fullness > 'd2) | data_ready_pre)) //burst end and data ready
|
HTRANS <= #1 TRANS_NONSEQ;
|
HTRANS <= #1 TRANS_NONSEQ;
|
else if (ahb_idle & ((data_fullness > 'd1) | data_ready_pre)) //bus idle and data ready
|
else if (ahb_idle & ((data_fullness > 'd1) | data_ready_pre)) //bus idle and data ready
|
HTRANS <= #1 TRANS_NONSEQ;
|
HTRANS <= #1 TRANS_NONSEQ;
|
else if (ahb_cmd_last)
|
else if (ahb_cmd_last)
|
HTRANS <= #1 TRANS_IDLE;
|
HTRANS <= #1 TRANS_IDLE;
|
else if (ahb_cmd & (data_fullness_pre <= 'd1) & (~data_ready_pre))
|
else if (ahb_cmd & (data_fullness_pre <= 'd1) & (~data_ready_pre))
|
HTRANS <= #1 TRANS_BUSY;
|
HTRANS <= #1 TRANS_BUSY;
|
else if (ahb_cmd | (ahb_busy & data_ready_pre))
|
else if (ahb_cmd | (ahb_busy & data_ready_pre))
|
HTRANS <= #1 TRANS_SEQ;
|
HTRANS <= #1 TRANS_SEQ;
|
|
|
always @(posedge clk or posedge reset)
|
always @(posedge clk or posedge reset)
|
if (reset)
|
if (reset)
|
begin
|
begin
|
wr_transfer_size_pre <= #1 {4{1'b0}};
|
wr_transfer_size_pre <= #1 {4{1'b0}};
|
wr_transfer_num_pre <= #1 3'd0;
|
wr_transfer_num_pre <= #1 3'd0;
|
end
|
end
|
else if (ahb_cmd)
|
else if (ahb_cmd)
|
begin
|
begin
|
wr_transfer_size_pre <= #1 data_width;
|
wr_transfer_size_pre <= #1 data_width;
|
wr_transfer_num_pre <= #1 wr_ch_num_out;
|
wr_transfer_num_pre <= #1 wr_ch_num_out;
|
end
|
end
|
|
|
prgen_delay #(1) delay_wr_transfer (.clk(clk), .reset(reset), .din(wr_transfer_pre), .dout(wr_transfer));
|
prgen_delay #(1) delay_wr_transfer (.clk(clk), .reset(reset), .din(wr_transfer_pre), .dout(wr_transfer));
|
|
|
always @(posedge clk or posedge reset)
|
always @(posedge clk or posedge reset)
|
if (reset)
|
if (reset)
|
begin
|
begin
|
wr_transfer_num <= #1 3'd0;
|
wr_transfer_num <= #1 3'd0;
|
wr_transfer_size <= #1 3'd0;
|
wr_transfer_size <= #1 3'd0;
|
end
|
end
|
else if (wr_transfer_pre)
|
else if (wr_transfer_pre)
|
begin
|
begin
|
wr_transfer_num <= #1 wr_transfer_num_pre;
|
wr_transfer_num <= #1 wr_transfer_num_pre;
|
wr_transfer_size <= #1 wr_transfer_size_pre;
|
wr_transfer_size <= #1 wr_transfer_size_pre;
|
end
|
end
|
|
|
always @(posedge clk or posedge reset)
|
always @(posedge clk or posedge reset)
|
if (reset)
|
if (reset)
|
wr_ch_num_resp <= #1 3'd0;
|
wr_ch_num_resp <= #1 3'd0;
|
else if (ahb_data_last)
|
else if (ahb_data_last)
|
wr_ch_num_resp <= #1 wr_transfer_num_pre;
|
wr_ch_num_resp <= #1 wr_transfer_num_pre;
|
|
|
|
|
prgen_fifo #(32+3+2+1+1+3+1+1, 2+1)
|
prgen_fifo #(32+3+2+1+1+3+1+1, 2+1)
|
cmd_fifo(
|
cmd_fifo(
|
.clk(clk),
|
.clk(clk),
|
.reset(reset),
|
.reset(reset),
|
.push(wr_burst_start),
|
.push(wr_burst_start),
|
.pop(ahb_cmd_last),
|
.pop(ahb_cmd_last),
|
.din({wr_burst_addr,
|
.din({wr_burst_addr,
|
HBURST_pre,
|
HBURST_pre,
|
HSIZE_pre,
|
HSIZE_pre,
|
wr_last_cmd,
|
wr_last_cmd,
|
wr_cmd_port,
|
wr_cmd_port,
|
wr_ch_num,
|
wr_ch_num,
|
joint_req,
|
joint_req,
|
cmd_single_in
|
cmd_single_in
|
}),
|
}),
|
.dout({HADDR_base,
|
.dout({HADDR_base,
|
HBURST,
|
HBURST,
|
HSIZE,
|
HSIZE,
|
wr_last_cmd_out,
|
wr_last_cmd_out,
|
wr_port_num,
|
wr_port_num,
|
wr_ch_num_out,
|
wr_ch_num_out,
|
joint_req_out,
|
joint_req_out,
|
cmd_single_out
|
cmd_single_out
|
}),
|
}),
|
.empty(cmd_empty),
|
.empty(cmd_empty),
|
.full(cmd_full)
|
.full(cmd_full)
|
);
|
);
|
|
|
|
|
prgen_fifo #(4+4+3+1, 2+1)
|
prgen_fifo #(4+4+3+1, 2+1)
|
cmd_data_fifo(
|
cmd_data_fifo(
|
.clk(clk),
|
.clk(clk),
|
.reset(reset),
|
.reset(reset),
|
.push(wr_burst_start),
|
.push(wr_burst_start),
|
.pop(ch_fifo_rd_last),
|
.pop(ch_fifo_rd_last),
|
.din({wr_next_size_in,
|
.din({wr_next_size_in,
|
data_num_pre,
|
data_num_pre,
|
wr_ch_num,
|
wr_ch_num,
|
wr_line_cmd
|
wr_line_cmd
|
}),
|
}),
|
.dout({wr_next_size,
|
.dout({wr_next_size,
|
data_num,
|
data_num,
|
ch_fifo_rd_num,
|
ch_fifo_rd_num,
|
wr_line_out
|
wr_line_out
|
}),
|
}),
|
.empty(cmd_data_empty),
|
.empty(cmd_data_empty),
|
.full(cmd_data_full)
|
.full(cmd_data_full)
|
);
|
);
|
|
|
|
|
assign port_change = 1'b0;
|
assign port_change = 1'b0;
|
assign port_change_end = 1'b0;
|
assign port_change_end = 1'b0;
|
|
|
|
|
assign data_fullness_pre = data_fullness + data_ready - wr_transfer_pre;
|
assign data_fullness_pre = data_fullness + data_ready - wr_transfer_pre;
|
|
|
always @(posedge clk or posedge reset)
|
always @(posedge clk or posedge reset)
|
if (reset)
|
if (reset)
|
data_fullness <= #1 3'd0;
|
data_fullness <= #1 3'd0;
|
else if (data_ready | wr_transfer_pre)
|
else if (data_ready | wr_transfer_pre)
|
data_fullness <= #1 data_fullness_pre;
|
data_fullness <= #1 data_fullness_pre;
|
|
|
always @(posedge clk or posedge reset)
|
always @(posedge clk or posedge reset)
|
if (reset)
|
if (reset)
|
data_on_the_way <= #1 2'd0;
|
data_on_the_way <= #1 2'd0;
|
else if (ch_fifo_rd | data_ready)
|
else if (ch_fifo_rd | data_ready)
|
data_on_the_way <= #1 data_on_the_way + ch_fifo_rd - data_ready;
|
data_on_the_way <= #1 data_on_the_way + ch_fifo_rd - data_ready;
|
|
|
assign data_pending_pre = ((data_fullness + data_on_the_way) > 'd3) & (~wr_transfer_pre);
|
assign data_pending_pre = ((data_fullness + data_on_the_way) > 'd3) & (~wr_transfer_pre);
|
|
|
prgen_delay #(1) delay_data_pending (.clk(clk), .reset(reset), .din(data_pending_pre), .dout(data_pending));
|
prgen_delay #(1) delay_data_pending (.clk(clk), .reset(reset), .din(data_pending_pre), .dout(data_pending));
|
|
|
//depth is set by maximum fifo read data latency
|
//depth is set by maximum fifo read data latency
|
prgen_fifo #(64, 5+2)
|
prgen_fifo #(64, 5+2)
|
data_fifo(
|
data_fifo(
|
.clk(clk),
|
.clk(clk),
|
.reset(reset),
|
.reset(reset),
|
.push(data_ready),
|
.push(data_ready),
|
.pop(wr_transfer_pre),
|
.pop(wr_transfer_pre),
|
.din(ch_fifo_rdata),
|
.din(ch_fifo_rdata),
|
.dout(HWDATA),
|
.dout(HWDATA),
|
.empty(data_empty),
|
.empty(data_empty),
|
.full(data_full)
|
.full(data_full)
|
);
|
);
|
|
|
|
|
dma_ahb64_core0_ahbm_timeout dma_ahb64_core0_ahbm_timeout (
|
dma_ahb64_core0_ahbm_timeout dma_ahb64_core0_ahbm_timeout (
|
.clk(clk),
|
.clk(clk),
|
.reset(reset),
|
.reset(reset),
|
.HTRANS(HTRANS),
|
.HTRANS(HTRANS),
|
.HREADY(HREADY),
|
.HREADY(HREADY),
|
.ahb_timeout(ahb_wr_timeout)
|
.ahb_timeout(ahb_wr_timeout)
|
);
|
);
|
|
|
assign ahb_wr_timeout_num = wr_ch_num_out;
|
assign ahb_wr_timeout_num = wr_ch_num_out;
|
|
|
|
|
|
|
endmodule
|
endmodule
|
|
|
|
|
|
|
|
|
|
|