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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Author: Eyal Hochberg ////
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//// eyal@provartec.com ////
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//// ////
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//// Downloaded from: http://www.opencores.org ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2010 Provartec LTD ////
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//// www.provartec.com ////
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//// info@provartec.com ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation.////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more////
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//// details. http://www.gnu.org/licenses/lgpl.html ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//---------------------------------------------------------
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//---------------------------------------------------------
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//-- File generated by RobustVerilog parser
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//-- File generated by RobustVerilog parser
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//-- Version: 1.0
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//-- Version: 1.0
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//-- Invoked Fri Mar 25 23:34:52 2011
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//-- Invoked Fri Mar 25 23:34:52 2011
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//--
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//--
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//-- Source file: dma_core_axim_cmd.v
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//-- Source file: dma_core_axim_cmd.v
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//---------------------------------------------------------
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//---------------------------------------------------------
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module dma_axi32_core0_axim_cmd(clk,reset,ch_num,burst_start,burst_addr,burst_size,end_line_cmd,extra_bit,cmd_port,joint_req,joint_pending,cmd_pending,cmd_full,cmd_split,cmd_num,cmd_line,page_cross,AID,AADDR,APORT,ALEN,ASIZE,AVALID,AREADY,AWVALID,AJOINT,axim_timeout_num,axim_timeout);
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module dma_axi32_core0_axim_cmd(clk,reset,ch_num,burst_start,burst_addr,burst_size,end_line_cmd,extra_bit,cmd_port,joint_req,joint_pending,cmd_pending,cmd_full,cmd_split,cmd_num,cmd_line,page_cross,AID,AADDR,APORT,ALEN,ASIZE,AVALID,AREADY,AWVALID,AJOINT,axim_timeout_num,axim_timeout);
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parameter AXI_WORD_SIZE = 1 ? 2'b10 : 2'b11;
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parameter AXI_WORD_SIZE = 1 ? 2'b10 : 2'b11;
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parameter AXI_2 = 1 ? 2 : 3;
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parameter AXI_2 = 1 ? 2 : 3;
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input clk;
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input clk;
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input reset;
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input reset;
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input [2:0] ch_num;
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input [2:0] ch_num;
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input burst_start;
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input burst_start;
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input [32-1:0] burst_addr;
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input [32-1:0] burst_addr;
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input [7-1:0] burst_size;
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input [7-1:0] burst_size;
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input end_line_cmd;
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input end_line_cmd;
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input extra_bit;
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input extra_bit;
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input cmd_port;
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input cmd_port;
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input joint_req;
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input joint_req;
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output joint_pending;
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output joint_pending;
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output cmd_pending;
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output cmd_pending;
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input cmd_full;
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input cmd_full;
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output cmd_split;
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output cmd_split;
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output [2:0] cmd_num;
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output [2:0] cmd_num;
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output cmd_line;
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output cmd_line;
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output page_cross;
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output page_cross;
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output [`CMD_BITS-1:0] AID;
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output [`CMD_BITS-1:0] AID;
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output [32-1:0] AADDR;
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output [32-1:0] AADDR;
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output APORT;
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output APORT;
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output [`LEN_BITS-1:0] ALEN;
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output [`LEN_BITS-1:0] ALEN;
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output [1:0] ASIZE;
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output [1:0] ASIZE;
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output AVALID;
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output AVALID;
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input AREADY;
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input AREADY;
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input AWVALID;
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input AWVALID;
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output AJOINT;
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output AJOINT;
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output [2:0] axim_timeout_num;
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output [2:0] axim_timeout_num;
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output axim_timeout;
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output axim_timeout;
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reg [`CMD_BITS-1:0] AID;
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reg [`CMD_BITS-1:0] AID;
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reg [`CMD_BITS-1:0] AID_reg;
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reg [`CMD_BITS-1:0] AID_reg;
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reg [32-1:0] AADDR;
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reg [32-1:0] AADDR;
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reg APORT;
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reg APORT;
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reg [`LEN_BITS-1:0] ALEN;
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reg [`LEN_BITS-1:0] ALEN;
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reg [1:0] ASIZE;
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reg [1:0] ASIZE;
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reg AVALID_reg;
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reg AVALID_reg;
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reg AJOINT;
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reg AJOINT;
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wire [`CMD_BITS-1:0] AID_pre;
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wire [`CMD_BITS-1:0] AID_pre;
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wire [32-1:0] AADDR_pre;
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wire [32-1:0] AADDR_pre;
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wire [1:0] ASIZE_pre;
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wire [1:0] ASIZE_pre;
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wire [`LEN_BITS-1:0] ALEN_pre;
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wire [`LEN_BITS-1:0] ALEN_pre;
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wire [7-1:0] burst_length;
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wire [7-1:0] burst_length;
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wire cmd;
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wire cmd;
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reg cmd_pending;
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reg cmd_pending;
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wire cmd_line_pre;
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wire cmd_line_pre;
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wire cmd_line;
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wire cmd_line;
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wire high_addr_pre;
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wire high_addr_pre;
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wire high_addr;
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wire high_addr;
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wire [8:0] burst_reach_pre;
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wire [8:0] burst_reach_pre;
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reg [8:0] burst_reach;
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reg [8:0] burst_reach;
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reg joint_cross;
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reg joint_cross;
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wire page_cross_pre;
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wire page_cross_pre;
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wire page_cross;
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wire page_cross;
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wire cross_start;
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wire cross_start;
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wire cross_start_d;
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wire cross_start_d;
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wire [8:0] max_burst;
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wire [8:0] max_burst;
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reg [8:0] max_burst_d;
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reg [8:0] max_burst_d;
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reg next_burst;
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reg next_burst;
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reg [7-1:0] next_burst_size;
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reg [7-1:0] next_burst_size;
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wire next_burst_start;
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wire next_burst_start;
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assign high_addr_pre = burst_addr[11:8] == 4'hf;
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assign high_addr_pre = burst_addr[11:8] == 4'hf;
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assign burst_reach_pre = burst_addr[7:0] + burst_size;
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assign burst_reach_pre = burst_addr[7:0] + burst_size;
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assign page_cross = high_addr & (burst_reach > {1'b1, {8{1'b0}}});
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assign page_cross = high_addr & (burst_reach > {1'b1, {8{1'b0}}});
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assign max_burst = {1'b1, {8{1'b0}}} - burst_addr[7:0];
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assign max_burst = {1'b1, {8{1'b0}}} - burst_addr[7:0];
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assign next_burst_start = next_burst & (~AVALID_reg) & (~cmd_full);
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assign next_burst_start = next_burst & (~AVALID_reg) & (~cmd_full);
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assign cross_start = burst_start & page_cross;
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assign cross_start = burst_start & page_cross;
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prgen_delay #(1) delay_high_addr (.clk(clk), .reset(reset), .din(high_addr_pre), .dout(high_addr));
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prgen_delay #(1) delay_high_addr (.clk(clk), .reset(reset), .din(high_addr_pre), .dout(high_addr));
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prgen_delay #(1) delay_cross_start (.clk(clk), .reset(reset), .din(cross_start), .dout(cross_start_d));
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prgen_delay #(1) delay_cross_start (.clk(clk), .reset(reset), .din(cross_start), .dout(cross_start_d));
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always @(posedge clk or posedge reset)
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always @(posedge clk or posedge reset)
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if (reset)
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if (reset)
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burst_reach <= #1 {9{1'b0}};
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burst_reach <= #1 {9{1'b0}};
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else if (high_addr_pre)
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else if (high_addr_pre)
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burst_reach <= #1 burst_reach_pre;
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burst_reach <= #1 burst_reach_pre;
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always @(posedge clk or posedge reset)
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always @(posedge clk or posedge reset)
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if (reset)
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if (reset)
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next_burst <= #1 1'b0;
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next_burst <= #1 1'b0;
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else if (next_burst_start)
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else if (next_burst_start)
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next_burst <= #1 1'b0;
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next_burst <= #1 1'b0;
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else if (cross_start)
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else if (cross_start)
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next_burst <= #1 1'b1;
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next_burst <= #1 1'b1;
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always @(posedge clk or posedge reset)
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always @(posedge clk or posedge reset)
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if (reset)
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if (reset)
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max_burst_d <= #1 {9{1'b0}};
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max_burst_d <= #1 {9{1'b0}};
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else if (cross_start)
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else if (cross_start)
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max_burst_d <= #1 max_burst;
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max_burst_d <= #1 max_burst;
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always @(posedge clk or posedge reset)
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always @(posedge clk or posedge reset)
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if (reset)
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if (reset)
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next_burst_size <= #1 {7{1'b0}};
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next_burst_size <= #1 {7{1'b0}};
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else if (cross_start)
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else if (cross_start)
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next_burst_size <= #1 burst_size;
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next_burst_size <= #1 burst_size;
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else if (cross_start_d)
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else if (cross_start_d)
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next_burst_size <= #1 next_burst_size - max_burst_d;
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next_burst_size <= #1 next_burst_size - max_burst_d;
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assign cmd_split = cross_start_d;
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assign cmd_split = cross_start_d;
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assign cmd = AVALID & AREADY;
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assign cmd = AVALID & AREADY;
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assign cmd_num = AID[2:0];
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assign cmd_num = AID[2:0];
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assign cmd_line_pre = cmd & AID[6];
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assign cmd_line_pre = cmd & AID[6];
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assign joint_pending = AVALID & (~AREADY) & AJOINT;
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assign joint_pending = AVALID & (~AREADY) & AJOINT;
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always @(posedge clk or posedge reset)
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always @(posedge clk or posedge reset)
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if (reset)
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if (reset)
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cmd_pending <= #1 1'b0;
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cmd_pending <= #1 1'b0;
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else if (burst_start)
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else if (burst_start)
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cmd_pending <= #1 1'b1;
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cmd_pending <= #1 1'b1;
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else if (cmd & (~next_burst))
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else if (cmd & (~next_burst))
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cmd_pending <= #1 1'b0;
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cmd_pending <= #1 1'b0;
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prgen_delay #(1) delay_cmd_line (.clk(clk), .reset(reset), .din(cmd_line_pre), .dout(cmd_line));
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prgen_delay #(1) delay_cmd_line (.clk(clk), .reset(reset), .din(cmd_line_pre), .dout(cmd_line));
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assign AID_pre = {
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assign AID_pre = {
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end_line_cmd, //[6]
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end_line_cmd, //[6]
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ASIZE_pre[1:0], //[5:4]
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ASIZE_pre[1:0], //[5:4]
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extra_bit, //[3]
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extra_bit, //[3]
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ch_num[2:0] //[2:0]
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ch_num[2:0] //[2:0]
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};
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};
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assign AADDR_pre = burst_addr;
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assign AADDR_pre = burst_addr;
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assign ASIZE_pre =
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assign ASIZE_pre =
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burst_size == 'd1 ? 2'b00 :
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burst_size == 'd1 ? 2'b00 :
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burst_size == 'd2 ? 2'b01 :
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burst_size == 'd2 ? 2'b01 :
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burst_size == 'd4 ? 2'b10 :
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burst_size == 'd4 ? 2'b10 :
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AXI_WORD_SIZE;
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AXI_WORD_SIZE;
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assign burst_length =
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assign burst_length =
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next_burst ? next_burst_size :
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next_burst ? next_burst_size :
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page_cross ? max_burst : burst_size;
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page_cross ? max_burst : burst_size;
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assign ALEN_pre =
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assign ALEN_pre =
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burst_length[7-1:AXI_2] == 'd0 ? {`LEN_BITS{1'b0}} :
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burst_length[7-1:AXI_2] == 'd0 ? {`LEN_BITS{1'b0}} :
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burst_length[7-1:AXI_2] - 1'b1;
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burst_length[7-1:AXI_2] - 1'b1;
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always @(posedge clk or posedge reset)
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always @(posedge clk or posedge reset)
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if (reset)
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if (reset)
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begin
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begin
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ASIZE <= #1 {2{1'b0}};
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ASIZE <= #1 {2{1'b0}};
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AJOINT <= #1 1'b0;
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AJOINT <= #1 1'b0;
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end
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end
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else if (burst_start)
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else if (burst_start)
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begin
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begin
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ASIZE <= #1 ASIZE_pre;
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ASIZE <= #1 ASIZE_pre;
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AJOINT <= #1 joint_req;
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AJOINT <= #1 joint_req;
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end
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end
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always @(posedge clk or posedge reset)
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always @(posedge clk or posedge reset)
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if (reset)
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if (reset)
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AID_reg <= #1 {`CMD_BITS{1'b0}};
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AID_reg <= #1 {`CMD_BITS{1'b0}};
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else if (burst_start)
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else if (burst_start)
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AID_reg <= #1 AID_pre;
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AID_reg <= #1 AID_pre;
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always @(AID_reg or next_burst)
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always @(AID_reg or next_burst)
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begin
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begin
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AID = AID_reg;
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AID = AID_reg;
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AID[`ID_END_LINE] = AID_reg[`ID_END_LINE] & (~next_burst);
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AID[`ID_END_LINE] = AID_reg[`ID_END_LINE] & (~next_burst);
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AID[`ID_LAST] = AID_reg[`ID_LAST] & (~next_burst);
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AID[`ID_LAST] = AID_reg[`ID_LAST] & (~next_burst);
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end
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end
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always @(posedge clk or posedge reset)
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always @(posedge clk or posedge reset)
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if (reset)
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if (reset)
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AADDR <= #1 {32{1'b0}};
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AADDR <= #1 {32{1'b0}};
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else if (next_burst_start)
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else if (next_burst_start)
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AADDR <= #1 {AADDR[32-1:12], {12{1'b1}}} + 1'b1;
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AADDR <= #1 {AADDR[32-1:12], {12{1'b1}}} + 1'b1;
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else if (burst_start)
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else if (burst_start)
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AADDR <= #1 AADDR_pre;
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AADDR <= #1 AADDR_pre;
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always @(posedge clk or posedge reset)
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always @(posedge clk or posedge reset)
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if (reset)
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if (reset)
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APORT <= #1 1'b0;
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APORT <= #1 1'b0;
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else if (burst_start)
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else if (burst_start)
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APORT <= #1 cmd_port;
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APORT <= #1 cmd_port;
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always @(posedge clk or posedge reset)
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always @(posedge clk or posedge reset)
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if (reset)
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if (reset)
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ALEN <= #1 {`LEN_BITS{1'b0}};
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ALEN <= #1 {`LEN_BITS{1'b0}};
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else if (burst_start | next_burst_start)
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else if (burst_start | next_burst_start)
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ALEN <= #1 ALEN_pre;
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ALEN <= #1 ALEN_pre;
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always @(posedge clk or posedge reset)
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always @(posedge clk or posedge reset)
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if (reset)
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if (reset)
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AVALID_reg <= #1 1'b0;
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AVALID_reg <= #1 1'b0;
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else if (AVALID & AREADY)
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else if (AVALID & AREADY)
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AVALID_reg <= #1 1'b0;
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AVALID_reg <= #1 1'b0;
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else if ((burst_start & (burst_size > 'd0)) | next_burst_start)
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else if ((burst_start & (burst_size > 'd0)) | next_burst_start)
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AVALID_reg <= #1 1'b1;
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AVALID_reg <= #1 1'b1;
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assign AVALID = AJOINT ? AVALID_reg & (~AWVALID) : AVALID_reg;
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assign AVALID = AJOINT ? AVALID_reg & (~AWVALID) : AVALID_reg;
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dma_axi32_core0_axim_timeout dma_axi32_axim_timeout (
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dma_axi32_core0_axim_timeout dma_axi32_axim_timeout (
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.clk(clk),
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.clk(clk),
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.reset(reset),
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.reset(reset),
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.VALID(AVALID),
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.VALID(AVALID),
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.READY(AREADY),
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.READY(AREADY),
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.ID(AID),
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.ID(AID),
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.axim_timeout_num(axim_timeout_num),
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.axim_timeout_num(axim_timeout_num),
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.axim_timeout(axim_timeout)
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.axim_timeout(axim_timeout)
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);
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);
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endmodule
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endmodule
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