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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Author: Eyal Hochberg ////
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//// eyal@provartec.com ////
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//// ////
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//// Downloaded from: http://www.opencores.org ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2010 Provartec LTD ////
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//// www.provartec.com ////
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//// info@provartec.com ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation.////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more////
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//// details. http://www.gnu.org/licenses/lgpl.html ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//---------------------------------------------------------
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//---------------------------------------------------------
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//-- File generated by RobustVerilog parser
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//-- File generated by RobustVerilog parser
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//-- Version: 1.0
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//-- Version: 1.0
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//-- Invoked Fri Mar 25 23:34:51 2011
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//-- Invoked Fri Mar 25 23:34:51 2011
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//--
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//--
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//-- Source file: dma_core_axim_rd.v
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//-- Source file: dma_core_axim_rd.v
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//---------------------------------------------------------
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//---------------------------------------------------------
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module dma_axi32_core0_axim_rd(clk,reset,load_wr,load_wr_num,load_wr_cycle,load_wdata,joint_stall,joint_req,rd_line_cmd,load_req_in_prog,rd_cmd_port,rd_ch_num,rd_burst_start,rd_burst_addr,rd_burst_size,rd_cmd_pending,rd_cmd_split,rd_cmd_line,rd_cmd_num,rd_cmd_full,ch_fifo_wr,ch_fifo_wdata,ch_fifo_wsize,ch_fifo_wr_num,rd_transfer_num,rd_transfer,rd_transfer_size,rd_burst_cmd,rd_clr_line,rd_clr_line_num,rd_slverr,rd_decerr,rd_clr,rd_clr_load,rd_clr_last,rd_ch_num_resp,page_cross,ARADDR,ARPORT,ARLEN,ARSIZE,ARVALID,ARREADY,AWVALID,RDATA,RRESP,RLAST,RVALID,RREADY_out,axim_timeout_ar,axim_timeout_num_ar);
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module dma_axi32_core0_axim_rd(clk,reset,load_wr,load_wr_num,load_wr_cycle,load_wdata,joint_stall,joint_req,rd_line_cmd,load_req_in_prog,rd_cmd_port,rd_ch_num,rd_burst_start,rd_burst_addr,rd_burst_size,rd_cmd_pending,rd_cmd_split,rd_cmd_line,rd_cmd_num,rd_cmd_full,ch_fifo_wr,ch_fifo_wdata,ch_fifo_wsize,ch_fifo_wr_num,rd_transfer_num,rd_transfer,rd_transfer_size,rd_burst_cmd,rd_clr_line,rd_clr_line_num,rd_slverr,rd_decerr,rd_clr,rd_clr_load,rd_clr_last,rd_ch_num_resp,page_cross,ARADDR,ARPORT,ARLEN,ARSIZE,ARVALID,ARREADY,AWVALID,RDATA,RRESP,RLAST,RVALID,RREADY_out,axim_timeout_ar,axim_timeout_num_ar);
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input clk;
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input clk;
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input reset;
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input reset;
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output load_wr;
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output load_wr;
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output [2:0] load_wr_num;
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output [2:0] load_wr_num;
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output [1:0] load_wr_cycle;
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output [1:0] load_wr_cycle;
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output [32-1:0] load_wdata;
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output [32-1:0] load_wdata;
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input joint_stall;
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input joint_stall;
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input joint_req;
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input joint_req;
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//command
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//command
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input rd_line_cmd;
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input rd_line_cmd;
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input load_req_in_prog;
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input load_req_in_prog;
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input rd_cmd_port;
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input rd_cmd_port;
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input [2:0] rd_ch_num;
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input [2:0] rd_ch_num;
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input rd_burst_start;
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input rd_burst_start;
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input [32-1:0] rd_burst_addr;
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input [32-1:0] rd_burst_addr;
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input [7-1:0] rd_burst_size;
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input [7-1:0] rd_burst_size;
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output rd_cmd_pending;
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output rd_cmd_pending;
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output rd_cmd_split;
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output rd_cmd_split;
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output rd_cmd_line;
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output rd_cmd_line;
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output [2:0] rd_cmd_num;
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output [2:0] rd_cmd_num;
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output rd_cmd_full;
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output rd_cmd_full;
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//data
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//data
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output ch_fifo_wr;
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output ch_fifo_wr;
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output [32-1:0] ch_fifo_wdata;
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output [32-1:0] ch_fifo_wdata;
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output [3-1:0] ch_fifo_wsize;
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output [3-1:0] ch_fifo_wsize;
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output [2:0] ch_fifo_wr_num;
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output [2:0] ch_fifo_wr_num;
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output [2:0] rd_transfer_num;
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output [2:0] rd_transfer_num;
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output rd_transfer;
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output rd_transfer;
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output [3-1:0] rd_transfer_size;
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output [3-1:0] rd_transfer_size;
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output rd_burst_cmd;
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output rd_burst_cmd;
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output rd_clr_line;
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output rd_clr_line;
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output [2:0] rd_clr_line_num;
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output [2:0] rd_clr_line_num;
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//resp
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//resp
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output rd_slverr;
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output rd_slverr;
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output rd_decerr;
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output rd_decerr;
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output rd_clr;
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output rd_clr;
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output rd_clr_load;
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output rd_clr_load;
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output rd_clr_last;
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output rd_clr_last;
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output [2:0] rd_ch_num_resp;
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output [2:0] rd_ch_num_resp;
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output page_cross;
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output page_cross;
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output [32-1:0] ARADDR;
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output [32-1:0] ARADDR;
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output ARPORT;
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output ARPORT;
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output [`LEN_BITS-1:0] ARLEN;
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output [`LEN_BITS-1:0] ARLEN;
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output [1:0] ARSIZE;
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output [1:0] ARSIZE;
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output ARVALID;
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output ARVALID;
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input ARREADY;
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input ARREADY;
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input AWVALID;
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input AWVALID;
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input [32-1:0] RDATA;
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input [32-1:0] RDATA;
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input [1:0] RRESP;
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input [1:0] RRESP;
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input RLAST;
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input RLAST;
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input RVALID;
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input RVALID;
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output RREADY_out;
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output RREADY_out;
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output axim_timeout_ar;
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output axim_timeout_ar;
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output [2:0] axim_timeout_num_ar;
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output [2:0] axim_timeout_num_ar;
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wire [`CMD_BITS-1:0] ARID;
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wire [`CMD_BITS-1:0] ARID;
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wire RVALID_d;
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wire RVALID_d;
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wire [`CMD_BITS-1:0] RID;
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wire [`CMD_BITS-1:0] RID;
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reg [32-1:0] RDATA_d;
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reg [32-1:0] RDATA_d;
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reg [1:0] RRESP_d;
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reg [1:0] RRESP_d;
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reg RLAST_d;
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reg RLAST_d;
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reg [3-1:0] rd_transfer_size;
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reg [3-1:0] rd_transfer_size;
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wire rd_clr_pre;
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wire rd_clr_pre;
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wire RREADY;
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wire RREADY;
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//don't give peripheral clr on cmd read
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//don't give peripheral clr on cmd read
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assign rd_clr = rd_clr_pre & (~rd_clr_last);
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assign rd_clr = rd_clr_pre & (~rd_clr_last);
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assign rd_clr_load = rd_clr_pre & rd_clr_last;
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assign rd_clr_load = rd_clr_pre & rd_clr_last;
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prgen_delay #(1) delay_ready(.clk(clk), .reset(reset), .din(RREADY_out), .dout(RREADY));
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prgen_delay #(1) delay_ready(.clk(clk), .reset(reset), .din(RREADY_out), .dout(RREADY));
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prgen_delay #(1) delay_rvalid(.clk(clk), .reset(reset), .din(RVALID), .dout(RVALID_d));
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prgen_delay #(1) delay_rvalid(.clk(clk), .reset(reset), .din(RVALID), .dout(RVALID_d));
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always @(posedge clk or posedge reset)
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always @(posedge clk or posedge reset)
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if (reset)
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if (reset)
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begin
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begin
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RRESP_d <= #1 2'b00;
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RRESP_d <= #1 2'b00;
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RDATA_d <= #1 {32{1'b0}};
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RDATA_d <= #1 {32{1'b0}};
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RLAST_d <= #1 1'b0;
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RLAST_d <= #1 1'b0;
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end
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end
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else if (RVALID)
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else if (RVALID)
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begin
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begin
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RRESP_d <= #1 RRESP;
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RRESP_d <= #1 RRESP;
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RDATA_d <= #1 RDATA;
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RDATA_d <= #1 RDATA;
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RLAST_d <= #1 RLAST;
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RLAST_d <= #1 RLAST;
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end
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end
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always @(/*AUTOSENSE*/RID)
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always @(/*AUTOSENSE*/RID)
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begin
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begin
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case (RID[5:4])
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case (RID[5:4])
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2'b00 : rd_transfer_size = 4'd1;
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2'b00 : rd_transfer_size = 4'd1;
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2'b01 : rd_transfer_size = 4'd2;
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2'b01 : rd_transfer_size = 4'd2;
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2'b10 : rd_transfer_size = 4'd4;
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2'b10 : rd_transfer_size = 4'd4;
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2'b11 : rd_transfer_size = 4'd8;
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2'b11 : rd_transfer_size = 4'd8;
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endcase
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endcase
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end
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end
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dma_axi32_core0_axim_cmd
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dma_axi32_core0_axim_cmd
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dma_axi32_axim_rcmd (
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dma_axi32_axim_rcmd (
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.clk(clk),
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.clk(clk),
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.reset(reset),
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.reset(reset),
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.end_line_cmd(rd_line_cmd),
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.end_line_cmd(rd_line_cmd),
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.extra_bit(load_req_in_prog),
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.extra_bit(load_req_in_prog),
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.cmd_port(rd_cmd_port),
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.cmd_port(rd_cmd_port),
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.ch_num(rd_ch_num),
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.ch_num(rd_ch_num),
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.joint_req(joint_req),
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.joint_req(joint_req),
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.burst_start(rd_burst_start),
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.burst_start(rd_burst_start),
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.burst_addr(rd_burst_addr),
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.burst_addr(rd_burst_addr),
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.burst_size(rd_burst_size),
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.burst_size(rd_burst_size),
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.cmd_pending(rd_cmd_pending),
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.cmd_pending(rd_cmd_pending),
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.cmd_full(rd_cmd_full),
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.cmd_full(rd_cmd_full),
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.cmd_split(rd_cmd_split),
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.cmd_split(rd_cmd_split),
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.cmd_num(rd_cmd_num),
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.cmd_num(rd_cmd_num),
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.cmd_line(rd_cmd_line),
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.cmd_line(rd_cmd_line),
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.page_cross(page_cross),
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.page_cross(page_cross),
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.AID(ARID),
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.AID(ARID),
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.AADDR(ARADDR),
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.AADDR(ARADDR),
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.APORT(ARPORT),
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.APORT(ARPORT),
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.ALEN(ARLEN),
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.ALEN(ARLEN),
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.ASIZE(ARSIZE),
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.ASIZE(ARSIZE),
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.AVALID(ARVALID),
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.AVALID(ARVALID),
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.AREADY(ARREADY),
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.AREADY(ARREADY),
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.AWVALID(AWVALID),
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.AWVALID(AWVALID),
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.AJOINT(),
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.AJOINT(),
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.axim_timeout_num(axim_timeout_num_ar),
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.axim_timeout_num(axim_timeout_num_ar),
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.axim_timeout(axim_timeout_ar)
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.axim_timeout(axim_timeout_ar)
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);
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);
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dma_axi32_core0_axim_rdata
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dma_axi32_core0_axim_rdata
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dma_axi32_axim_rdata (
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dma_axi32_axim_rdata (
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.clk(clk),
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.clk(clk),
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.reset(reset),
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.reset(reset),
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.load_wr(load_wr),
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.load_wr(load_wr),
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.load_wr_num(load_wr_num),
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.load_wr_num(load_wr_num),
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.load_wr_cycle(load_wr_cycle),
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.load_wr_cycle(load_wr_cycle),
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.load_wdata(load_wdata),
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.load_wdata(load_wdata),
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.joint_stall(joint_stall),
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.joint_stall(joint_stall),
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.ch_fifo_wr(ch_fifo_wr),
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.ch_fifo_wr(ch_fifo_wr),
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.ch_fifo_wdata(ch_fifo_wdata),
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.ch_fifo_wdata(ch_fifo_wdata),
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.ch_fifo_wsize(ch_fifo_wsize),
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.ch_fifo_wsize(ch_fifo_wsize),
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.ch_fifo_wr_num(ch_fifo_wr_num),
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.ch_fifo_wr_num(ch_fifo_wr_num),
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.rd_transfer_num(rd_transfer_num),
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.rd_transfer_num(rd_transfer_num),
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.rd_transfer(rd_transfer),
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.rd_transfer(rd_transfer),
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.rd_transfer_size(rd_transfer_size),
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.rd_transfer_size(rd_transfer_size),
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.rd_clr_line(rd_clr_line),
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.rd_clr_line(rd_clr_line),
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.rd_clr_line_num(rd_clr_line_num),
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.rd_clr_line_num(rd_clr_line_num),
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.rd_burst_cmd(rd_burst_cmd),
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.rd_burst_cmd(rd_burst_cmd),
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.ARVALID(ARVALID),
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.ARVALID(ARVALID),
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.ARREADY(ARREADY),
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.ARREADY(ARREADY),
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.ARID(ARID),
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.ARID(ARID),
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.RID(RID),
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.RID(RID),
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.RDATA(RDATA_d),
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.RDATA(RDATA_d),
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.RLAST(RLAST_d),
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.RLAST(RLAST_d),
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.RVALID(RVALID_d),
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.RVALID(RVALID_d),
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.RREADY(RREADY),
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.RREADY(RREADY),
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.RREADY_out(RREADY_out)
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.RREADY_out(RREADY_out)
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);
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);
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dma_axi32_core0_axim_resp #(.CMD_DEPTH(2))
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dma_axi32_core0_axim_resp #(.CMD_DEPTH(2))
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dma_axi32_axim_rresp (
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dma_axi32_axim_rresp (
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.clk(clk),
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.clk(clk),
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.reset(reset),
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.reset(reset),
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.slverr(rd_slverr),
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.slverr(rd_slverr),
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.decerr(rd_decerr),
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.decerr(rd_decerr),
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.clr(rd_clr_pre),
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.clr(rd_clr_pre),
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.clr_last(rd_clr_last),
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.clr_last(rd_clr_last),
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.ch_num_resp(rd_ch_num_resp),
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.ch_num_resp(rd_ch_num_resp),
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.resp_full(rd_cmd_full),
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.resp_full(rd_cmd_full),
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.AID(ARID),
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.AID(ARID),
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.AVALID(ARVALID),
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.AVALID(ARVALID),
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.AREADY(ARREADY),
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.AREADY(ARREADY),
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.ID(RID),
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.ID(RID),
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.RESP(RRESP_d),
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.RESP(RRESP_d),
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.VALID(RVALID_d),
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.VALID(RVALID_d),
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.READY(RREADY),
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.READY(RREADY),
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.LAST(RLAST_d)
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.LAST(RLAST_d)
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);
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);
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endmodule
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endmodule
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