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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Author: Eyal Hochberg ////
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//// eyal@provartec.com ////
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//// ////
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//// Downloaded from: http://www.opencores.org ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2010 Provartec LTD ////
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//// www.provartec.com ////
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//// info@provartec.com ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation.////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more////
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//// details. http://www.gnu.org/licenses/lgpl.html ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//---------------------------------------------------------
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//---------------------------------------------------------
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//-- File generated by RobustVerilog parser
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//-- File generated by RobustVerilog parser
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//-- Version: 1.0
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//-- Version: 1.0
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//-- Invoked Fri Mar 25 23:34:51 2011
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//-- Invoked Fri Mar 25 23:34:51 2011
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//--
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//--
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//-- Source file: dma_core_axim_wr.v
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//-- Source file: dma_core_axim_wr.v
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//---------------------------------------------------------
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//---------------------------------------------------------
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module dma_axi32_core0_axim_wr(clk,reset,wr_cmd_port,wr_last_cmd,wr_line_cmd,wr_ch_num,wr_burst_start,wr_burst_addr,wr_burst_size,wr_cmd_pending,wr_cmd_split,wr_cmd_num,rd_transfer,rd_transfer_size,ch_fifo_rd,ch_fifo_rdata,ch_fifo_rd_valid,ch_fifo_rsize,ch_fifo_wr_ready,ch_fifo_rd_num,wr_transfer_num,wr_transfer,wr_transfer_size,wr_next_size,wr_cmd_full,wr_clr_line,wr_clr_line_num,wr_slverr,wr_decerr,wr_clr,wr_clr_last,wr_ch_num_resp,page_cross,AWADDR,AWPORT,AWLEN,AWSIZE,AWVALID,AWREADY,WDATA,WSTRB,WLAST,WVALID,WREADY,BRESP,BVALID,BREADY,joint_req,joint_stall,axim_timeout_aw,axim_timeout_w,axim_timeout_num_aw,axim_timeout_num_w);
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module dma_axi32_core0_axim_wr(clk,reset,wr_cmd_port,wr_last_cmd,wr_line_cmd,wr_ch_num,wr_burst_start,wr_burst_addr,wr_burst_size,wr_cmd_pending,wr_cmd_split,wr_cmd_num,rd_transfer,rd_transfer_size,ch_fifo_rd,ch_fifo_rdata,ch_fifo_rd_valid,ch_fifo_rsize,ch_fifo_wr_ready,ch_fifo_rd_num,wr_transfer_num,wr_transfer,wr_transfer_size,wr_next_size,wr_cmd_full,wr_clr_line,wr_clr_line_num,wr_slverr,wr_decerr,wr_clr,wr_clr_last,wr_ch_num_resp,page_cross,AWADDR,AWPORT,AWLEN,AWSIZE,AWVALID,AWREADY,WDATA,WSTRB,WLAST,WVALID,WREADY,BRESP,BVALID,BREADY,joint_req,joint_stall,axim_timeout_aw,axim_timeout_w,axim_timeout_num_aw,axim_timeout_num_w);
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input clk;
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input clk;
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input reset;
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input reset;
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//command
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//command
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input wr_cmd_port;
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input wr_cmd_port;
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input wr_last_cmd;
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input wr_last_cmd;
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input wr_line_cmd;
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input wr_line_cmd;
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input [2:0] wr_ch_num;
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input [2:0] wr_ch_num;
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input wr_burst_start;
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input wr_burst_start;
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input [32-1:0] wr_burst_addr;
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input [32-1:0] wr_burst_addr;
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input [7-1:0] wr_burst_size;
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input [7-1:0] wr_burst_size;
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output wr_cmd_pending;
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output wr_cmd_pending;
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output wr_cmd_split;
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output wr_cmd_split;
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output [2:0] wr_cmd_num;
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output [2:0] wr_cmd_num;
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//data
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//data
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input rd_transfer;
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input rd_transfer;
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input [3-1:0] rd_transfer_size;
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input [3-1:0] rd_transfer_size;
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output ch_fifo_rd;
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output ch_fifo_rd;
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input [32-1:0] ch_fifo_rdata;
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input [32-1:0] ch_fifo_rdata;
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input ch_fifo_rd_valid;
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input ch_fifo_rd_valid;
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output [3-1:0] ch_fifo_rsize;
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output [3-1:0] ch_fifo_rsize;
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input ch_fifo_wr_ready;
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input ch_fifo_wr_ready;
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output [2:0] ch_fifo_rd_num;
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output [2:0] ch_fifo_rd_num;
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output [2:0] wr_transfer_num;
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output [2:0] wr_transfer_num;
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output wr_transfer;
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output wr_transfer;
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output [3-1:0] wr_transfer_size;
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output [3-1:0] wr_transfer_size;
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output [3-1:0] wr_next_size;
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output [3-1:0] wr_next_size;
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output wr_cmd_full;
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output wr_cmd_full;
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output wr_clr_line;
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output wr_clr_line;
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output [2:0] wr_clr_line_num;
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output [2:0] wr_clr_line_num;
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//resp
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//resp
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output wr_slverr;
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output wr_slverr;
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output wr_decerr;
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output wr_decerr;
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output wr_clr;
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output wr_clr;
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output wr_clr_last;
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output wr_clr_last;
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output [2:0] wr_ch_num_resp;
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output [2:0] wr_ch_num_resp;
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output page_cross;
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output page_cross;
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output [32-1:0] AWADDR;
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output [32-1:0] AWADDR;
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output AWPORT;
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output AWPORT;
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output [`LEN_BITS-1:0] AWLEN;
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output [`LEN_BITS-1:0] AWLEN;
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output [1:0] AWSIZE;
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output [1:0] AWSIZE;
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output AWVALID;
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output AWVALID;
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input AWREADY;
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input AWREADY;
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output [32-1:0] WDATA;
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output [32-1:0] WDATA;
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output [4-1:0] WSTRB;
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output [4-1:0] WSTRB;
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output WLAST;
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output WLAST;
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output WVALID;
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output WVALID;
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input WREADY;
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input WREADY;
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input [1:0] BRESP;
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input [1:0] BRESP;
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input BVALID;
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input BVALID;
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output BREADY;
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output BREADY;
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input joint_req;
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input joint_req;
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output joint_stall;
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output joint_stall;
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output axim_timeout_aw;
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output axim_timeout_aw;
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output axim_timeout_w;
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output axim_timeout_w;
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output [2:0] axim_timeout_num_aw;
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output [2:0] axim_timeout_num_aw;
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output [2:0] axim_timeout_num_w;
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output [2:0] axim_timeout_num_w;
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wire [`CMD_BITS-1:0] AWID;
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wire [`CMD_BITS-1:0] AWID;
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wire AJOINT;
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wire AJOINT;
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wire BVALID_d;
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wire BVALID_d;
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wire [`CMD_BITS-1:0] BID;
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wire [`CMD_BITS-1:0] BID;
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reg [1:0] BRESP_d;
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reg [1:0] BRESP_d;
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wire wr_resp_full;
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wire wr_resp_full;
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assign BREADY = 1'b1;
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assign BREADY = 1'b1;
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prgen_delay #(1) delay_bvalid(.clk(clk), .reset(reset), .din(BVALID), .dout(BVALID_d));
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prgen_delay #(1) delay_bvalid(.clk(clk), .reset(reset), .din(BVALID), .dout(BVALID_d));
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always @(posedge clk or posedge reset)
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always @(posedge clk or posedge reset)
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if (reset)
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if (reset)
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begin
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begin
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BRESP_d <= #1 2'b00;
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BRESP_d <= #1 2'b00;
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end
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end
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else if (BVALID)
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else if (BVALID)
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begin
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begin
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BRESP_d <= #1 BRESP;
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BRESP_d <= #1 BRESP;
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end
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end
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dma_axi32_core0_axim_cmd
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dma_axi32_core0_axim_cmd
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dma_axi32_axim_wcmd (
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dma_axi32_axim_wcmd (
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.clk(clk),
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.clk(clk),
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.reset(reset),
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.reset(reset),
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.end_line_cmd(wr_line_cmd),
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.end_line_cmd(wr_line_cmd),
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.extra_bit(wr_last_cmd),
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.extra_bit(wr_last_cmd),
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.cmd_port(wr_cmd_port),
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.cmd_port(wr_cmd_port),
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.joint_req(joint_req),
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.joint_req(joint_req),
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.ch_num(wr_ch_num),
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.ch_num(wr_ch_num),
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.burst_start(wr_burst_start),
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.burst_start(wr_burst_start),
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.burst_addr(wr_burst_addr),
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.burst_addr(wr_burst_addr),
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.burst_size(wr_burst_size),
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.burst_size(wr_burst_size),
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.cmd_pending(wr_cmd_pending),
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.cmd_pending(wr_cmd_pending),
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.cmd_full(wr_cmd_full),
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.cmd_full(wr_cmd_full),
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.cmd_split(wr_cmd_split),
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.cmd_split(wr_cmd_split),
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.cmd_num(wr_cmd_num),
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.cmd_num(wr_cmd_num),
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.cmd_line(),
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.cmd_line(),
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.page_cross(page_cross),
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.page_cross(page_cross),
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.AID(AWID),
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.AID(AWID),
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.AADDR(AWADDR),
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.AADDR(AWADDR),
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.APORT(AWPORT),
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.APORT(AWPORT),
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.ALEN(AWLEN),
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.ALEN(AWLEN),
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.ASIZE(AWSIZE),
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.ASIZE(AWSIZE),
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.AVALID(AWVALID),
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.AVALID(AWVALID),
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.AREADY(AWREADY),
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.AREADY(AWREADY),
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.AWVALID(1'b0),
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.AWVALID(1'b0),
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.AJOINT(AJOINT),
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.AJOINT(AJOINT),
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.axim_timeout_num(axim_timeout_num_aw),
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.axim_timeout_num(axim_timeout_num_aw),
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.axim_timeout(axim_timeout_aw)
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.axim_timeout(axim_timeout_aw)
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);
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);
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dma_axi32_core0_axim_wdata
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dma_axi32_core0_axim_wdata
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dma_axi32_axim_wdata (
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dma_axi32_axim_wdata (
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.clk(clk),
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.clk(clk),
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.reset(reset),
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.reset(reset),
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.joint_stall(joint_stall),
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.joint_stall(joint_stall),
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.rd_transfer(rd_transfer),
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.rd_transfer(rd_transfer),
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.rd_transfer_size(rd_transfer_size),
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.rd_transfer_size(rd_transfer_size),
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.ch_fifo_rd(ch_fifo_rd),
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.ch_fifo_rd(ch_fifo_rd),
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.ch_fifo_rdata(ch_fifo_rdata),
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.ch_fifo_rdata(ch_fifo_rdata),
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.ch_fifo_rd_valid(ch_fifo_rd_valid),
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.ch_fifo_rd_valid(ch_fifo_rd_valid),
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.ch_fifo_rsize(ch_fifo_rsize),
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.ch_fifo_rsize(ch_fifo_rsize),
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.ch_fifo_rd_num(ch_fifo_rd_num),
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.ch_fifo_rd_num(ch_fifo_rd_num),
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.ch_fifo_wr_ready(ch_fifo_wr_ready),
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.ch_fifo_wr_ready(ch_fifo_wr_ready),
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.wr_transfer_num(wr_transfer_num),
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.wr_transfer_num(wr_transfer_num),
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.wr_transfer(wr_transfer),
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.wr_transfer(wr_transfer),
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.wr_transfer_size(wr_transfer_size),
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.wr_transfer_size(wr_transfer_size),
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.wr_next_size(wr_next_size),
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.wr_next_size(wr_next_size),
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.wr_resp_full(wr_resp_full),
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.wr_resp_full(wr_resp_full),
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.wr_cmd_full(wr_cmd_full),
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.wr_cmd_full(wr_cmd_full),
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.wr_clr_line(wr_clr_line),
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.wr_clr_line(wr_clr_line),
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.wr_clr_line_num(wr_clr_line_num),
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.wr_clr_line_num(wr_clr_line_num),
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.AWID(AWID),
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.AWID(AWID),
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.AWADDR(AWADDR),
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.AWADDR(AWADDR),
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.AWLEN(AWLEN),
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.AWLEN(AWLEN),
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.AWSIZE(AWSIZE),
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.AWSIZE(AWSIZE),
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.AWVALID(AWVALID),
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.AWVALID(AWVALID),
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.AWREADY(AWREADY),
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.AWREADY(AWREADY),
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.AJOINT(AJOINT),
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.AJOINT(AJOINT),
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.WDATA(WDATA),
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.WDATA(WDATA),
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.WSTRB(WSTRB),
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.WSTRB(WSTRB),
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.WLAST(WLAST),
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.WLAST(WLAST),
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.WVALID(WVALID),
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.WVALID(WVALID),
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.WREADY(WREADY),
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.WREADY(WREADY),
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.axim_timeout_num(axim_timeout_num_w),
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.axim_timeout_num(axim_timeout_num_w),
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.axim_timeout(axim_timeout_w)
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.axim_timeout(axim_timeout_w)
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);
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);
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dma_axi32_core0_axim_resp #(.CMD_DEPTH(2))
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dma_axi32_core0_axim_resp #(.CMD_DEPTH(2))
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dma_axi32_axim_wresp (
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dma_axi32_axim_wresp (
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.clk(clk),
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.clk(clk),
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.reset(reset),
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.reset(reset),
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.slverr(wr_slverr),
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.slverr(wr_slverr),
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.decerr(wr_decerr),
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.decerr(wr_decerr),
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.clr(wr_clr),
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.clr(wr_clr),
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.clr_last(wr_clr_last),
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.clr_last(wr_clr_last),
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.ch_num_resp(wr_ch_num_resp),
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.ch_num_resp(wr_ch_num_resp),
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.resp_full(wr_resp_full),
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.resp_full(wr_resp_full),
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.AID(AWID),
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.AID(AWID),
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.AVALID(AWVALID),
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.AVALID(AWVALID),
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.AREADY(AWREADY),
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.AREADY(AWREADY),
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.ID(BID),
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.ID(BID),
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.RESP(BRESP_d),
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.RESP(BRESP_d),
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.VALID(BVALID_d),
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.VALID(BVALID_d),
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.READY(BREADY),
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.READY(BREADY),
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.LAST(1'b1)
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.LAST(1'b1)
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);
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);
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endmodule
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endmodule
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