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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Author: Eyal Hochberg ////
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//// eyal@provartec.com ////
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//// ////
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//// Downloaded from: http://www.opencores.org ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2010 Provartec LTD ////
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//// www.provartec.com ////
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//// info@provartec.com ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation.////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more////
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//// details. http://www.gnu.org/licenses/lgpl.html ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//---------------------------------------------------------
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//---------------------------------------------------------
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//-- File generated by RobustVerilog parser
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//-- File generated by RobustVerilog parser
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//-- Version: 1.0
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//-- Version: 1.0
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//-- Invoked Fri Mar 25 23:34:52 2011
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//-- Invoked Fri Mar 25 23:34:52 2011
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//--
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//--
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//-- Source file: dma_ch.v
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//-- Source file: dma_ch.v
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//---------------------------------------------------------
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//---------------------------------------------------------
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module dma_axi32_core0_ch (clk,reset,scan_en,pclk,clken,pclken,psel,penable,paddr,pwrite,pwdata,prdata,pslverr,periph_tx_req,periph_tx_clr,periph_rx_req,periph_rx_clr,rd_cmd_split,rd_cmd_line,rd_clr_line,rd_clr,rd_clr_load,rd_slverr,rd_decerr,wr_cmd_split,wr_cmd_pending,wr_clr_line,wr_clr,wr_clr_last,wr_slverr,wr_decerr,load_wr,load_wr_cycle,load_wdata,load_req_in_prog,int_all_proc,ch_start,idle,ch_active,ch_rd_active,ch_wr_active,wr_last_cmd,rd_line_cmd,wr_line_cmd,rd_go_next_line,wr_go_next_line,rd_ready,rd_burst_start,rd_burst_addr,rd_burst_size,rd_tokens,rd_port_num,rd_periph_delay,rd_clr_valid,rd_transfer,rd_transfer_size,rd_clr_stall,wr_ready,wr_burst_start,wr_burst_addr,wr_burst_size,wr_tokens,wr_port_num,wr_periph_delay,wr_clr_valid,wr_transfer,wr_transfer_size,wr_next_size,wr_clr_stall,wr_incr,timeout_aw,timeout_w,timeout_ar,wdt_timeout,fifo_wr,fifo_wdata,fifo_wsize,fifo_rd,fifo_rsize,fifo_rd_valid,fifo_rdata,fifo_wr_ready,joint_mode,joint_remote,rd_page_cross,wr_page_cross,joint_in_prog,joint_not_in_prog,joint_mux_in_prog,joint_req);
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module dma_axi32_core0_ch (clk,reset,scan_en,pclk,clken,pclken,psel,penable,paddr,pwrite,pwdata,prdata,pslverr,periph_tx_req,periph_tx_clr,periph_rx_req,periph_rx_clr,rd_cmd_split,rd_cmd_line,rd_clr_line,rd_clr,rd_clr_load,rd_slverr,rd_decerr,wr_cmd_split,wr_cmd_pending,wr_clr_line,wr_clr,wr_clr_last,wr_slverr,wr_decerr,load_wr,load_wr_cycle,load_wdata,load_req_in_prog,int_all_proc,ch_start,idle,ch_active,ch_rd_active,ch_wr_active,wr_last_cmd,rd_line_cmd,wr_line_cmd,rd_go_next_line,wr_go_next_line,rd_ready,rd_burst_start,rd_burst_addr,rd_burst_size,rd_tokens,rd_port_num,rd_periph_delay,rd_clr_valid,rd_transfer,rd_transfer_size,rd_clr_stall,wr_ready,wr_burst_start,wr_burst_addr,wr_burst_size,wr_tokens,wr_port_num,wr_periph_delay,wr_clr_valid,wr_transfer,wr_transfer_size,wr_next_size,wr_clr_stall,wr_incr,timeout_aw,timeout_w,timeout_ar,wdt_timeout,fifo_wr,fifo_wdata,fifo_wsize,fifo_rd,fifo_rsize,fifo_rd_valid,fifo_rdata,fifo_wr_ready,joint_mode,joint_remote,rd_page_cross,wr_page_cross,joint_in_prog,joint_not_in_prog,joint_mux_in_prog,joint_req);
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input clk;
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input clk;
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input reset;
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input reset;
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input scan_en;
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input scan_en;
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input pclk;
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input pclk;
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input clken;
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input clken;
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input pclken;
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input pclken;
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input psel;
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input psel;
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input penable;
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input penable;
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input [7:0] paddr;
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input [7:0] paddr;
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input pwrite;
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input pwrite;
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input [31:0] pwdata;
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input [31:0] pwdata;
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output [31:0] prdata;
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output [31:0] prdata;
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output pslverr;
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output pslverr;
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input [31:1] periph_tx_req;
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input [31:1] periph_tx_req;
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output [31:1] periph_tx_clr;
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output [31:1] periph_tx_clr;
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input [31:1] periph_rx_req;
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input [31:1] periph_rx_req;
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output [31:1] periph_rx_clr;
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output [31:1] periph_rx_clr;
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input rd_cmd_split;
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input rd_cmd_split;
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input rd_cmd_line;
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input rd_cmd_line;
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input rd_clr_line;
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input rd_clr_line;
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input rd_clr;
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input rd_clr;
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input rd_clr_load;
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input rd_clr_load;
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input rd_slverr;
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input rd_slverr;
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input rd_decerr;
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input rd_decerr;
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input wr_cmd_split;
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input wr_cmd_split;
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input wr_cmd_pending;
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input wr_cmd_pending;
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input wr_clr_line;
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input wr_clr_line;
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input wr_clr;
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input wr_clr;
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input wr_clr_last;
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input wr_clr_last;
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input wr_slverr;
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input wr_slverr;
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input wr_decerr;
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input wr_decerr;
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input load_wr;
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input load_wr;
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input [1:0] load_wr_cycle;
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input [1:0] load_wr_cycle;
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input [32-1:0] load_wdata;
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input [32-1:0] load_wdata;
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output load_req_in_prog;
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output load_req_in_prog;
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output [1-1:0] int_all_proc;
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output [1-1:0] int_all_proc;
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input ch_start;
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input ch_start;
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output idle;
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output idle;
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output ch_active;
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output ch_active;
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output ch_rd_active;
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output ch_rd_active;
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output ch_wr_active;
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output ch_wr_active;
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output wr_last_cmd;
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output wr_last_cmd;
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output rd_line_cmd;
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output rd_line_cmd;
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output wr_line_cmd;
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output wr_line_cmd;
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output rd_go_next_line;
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output rd_go_next_line;
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output wr_go_next_line;
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output wr_go_next_line;
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output rd_ready;
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output rd_ready;
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input rd_burst_start;
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input rd_burst_start;
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output [32-1:0] rd_burst_addr;
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output [32-1:0] rd_burst_addr;
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output [7-1:0] rd_burst_size;
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output [7-1:0] rd_burst_size;
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output [`TOKEN_BITS-1:0] rd_tokens;
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output [`TOKEN_BITS-1:0] rd_tokens;
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output rd_port_num;
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output rd_port_num;
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output [`DELAY_BITS-1:0] rd_periph_delay;
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output [`DELAY_BITS-1:0] rd_periph_delay;
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output rd_clr_valid;
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output rd_clr_valid;
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input rd_transfer;
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input rd_transfer;
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input [3-1:0] rd_transfer_size;
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input [3-1:0] rd_transfer_size;
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output rd_clr_stall;
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output rd_clr_stall;
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output wr_ready;
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output wr_ready;
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input wr_burst_start;
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input wr_burst_start;
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output [32-1:0] wr_burst_addr;
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output [32-1:0] wr_burst_addr;
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output [7-1:0] wr_burst_size;
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output [7-1:0] wr_burst_size;
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output [`TOKEN_BITS-1:0] wr_tokens;
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output [`TOKEN_BITS-1:0] wr_tokens;
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output wr_port_num;
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output wr_port_num;
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output [`DELAY_BITS-1:0] wr_periph_delay;
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output [`DELAY_BITS-1:0] wr_periph_delay;
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output wr_clr_valid;
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output wr_clr_valid;
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input wr_transfer;
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input wr_transfer;
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input [3-1:0] wr_transfer_size;
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input [3-1:0] wr_transfer_size;
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input [3-1:0] wr_next_size;
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input [3-1:0] wr_next_size;
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output wr_clr_stall;
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output wr_clr_stall;
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output wr_incr;
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output wr_incr;
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input timeout_aw;
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input timeout_aw;
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input timeout_w;
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input timeout_w;
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input timeout_ar;
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input timeout_ar;
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input wdt_timeout;
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input wdt_timeout;
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input fifo_wr;
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input fifo_wr;
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input [32-1:0] fifo_wdata;
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input [32-1:0] fifo_wdata;
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input [3-1:0] fifo_wsize;
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input [3-1:0] fifo_wsize;
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input fifo_rd;
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input fifo_rd;
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input [3-1:0] fifo_rsize;
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input [3-1:0] fifo_rsize;
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output fifo_rd_valid;
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output fifo_rd_valid;
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output [32-1:0] fifo_rdata;
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output [32-1:0] fifo_rdata;
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output fifo_wr_ready;
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output fifo_wr_ready;
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input joint_mode;
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input joint_mode;
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input joint_remote;
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input joint_remote;
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input rd_page_cross;
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input rd_page_cross;
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input wr_page_cross;
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input wr_page_cross;
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output joint_in_prog;
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output joint_in_prog;
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output joint_not_in_prog;
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output joint_not_in_prog;
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output joint_mux_in_prog;
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output joint_mux_in_prog;
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output joint_req;
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output joint_req;
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//outputs of reg
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//outputs of reg
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wire [32-1:0] load_addr;
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wire [32-1:0] load_addr;
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wire load_in_prog;
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wire load_in_prog;
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wire load_req_in_prog;
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wire load_req_in_prog;
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wire ch_update;
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wire ch_update;
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wire [32-1:0] rd_start_addr;
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wire [32-1:0] rd_start_addr;
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wire [32-1:0] wr_start_addr;
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wire [32-1:0] wr_start_addr;
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wire [10-1:0] x_size;
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wire [10-1:0] x_size;
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wire [10-`X_BITS-1:0] y_size;
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wire [10-`X_BITS-1:0] y_size;
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wire block;
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wire block;
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wire joint;
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wire joint;
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wire [`FRAME_BITS-1:0] frame_width;
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wire [`FRAME_BITS-1:0] frame_width;
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wire [2-1:0] width_align;
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wire [2-1:0] width_align;
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wire [`DELAY_BITS-1:0] rd_periph_delay;
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wire [`DELAY_BITS-1:0] rd_periph_delay;
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wire [`DELAY_BITS-1:0] wr_periph_delay;
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wire [`DELAY_BITS-1:0] wr_periph_delay;
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wire rd_periph_block;
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wire rd_periph_block;
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wire wr_periph_block;
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wire wr_periph_block;
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wire [`TOKEN_BITS-1:0] rd_tokens;
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wire [`TOKEN_BITS-1:0] rd_tokens;
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wire [`TOKEN_BITS-1:0] wr_tokens;
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wire [`TOKEN_BITS-1:0] wr_tokens;
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wire rd_port_num;
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wire rd_port_num;
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wire wr_port_num;
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wire wr_port_num;
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wire [`OUT_BITS-1:0] rd_outs_max;
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wire [`OUT_BITS-1:0] rd_outs_max;
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wire [`OUT_BITS-1:0] wr_outs_max;
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wire [`OUT_BITS-1:0] wr_outs_max;
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wire [`WAIT_BITS-1:0] rd_wait_limit;
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wire [`WAIT_BITS-1:0] rd_wait_limit;
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wire [`WAIT_BITS-1:0] wr_wait_limit;
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wire [`WAIT_BITS-1:0] wr_wait_limit;
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wire rd_incr;
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wire rd_incr;
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wire wr_incr;
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wire wr_incr;
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wire [7-1:0] rd_burst_max_size;
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wire [7-1:0] rd_burst_max_size;
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wire [7-1:0] wr_burst_max_size;
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wire [7-1:0] wr_burst_max_size;
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wire [4:0] rd_periph_num;
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wire [4:0] rd_periph_num;
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wire [4:0] wr_periph_num;
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wire [4:0] wr_periph_num;
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wire wr_outstanding;
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wire wr_outstanding;
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wire rd_outstanding;
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wire rd_outstanding;
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wire ch_retry_wait;
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wire ch_retry_wait;
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wire ch_rd_active;
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wire ch_rd_active;
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wire ch_wr_active;
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wire ch_wr_active;
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wire ch_in_prog;
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wire ch_in_prog;
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wire [1:0] end_swap;
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wire [1:0] end_swap;
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//outputs of rd offsets
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//outputs of rd offsets
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wire [10-1:0] rd_x_offset;
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wire [10-1:0] rd_x_offset;
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wire [10-`X_BITS-1:0] rd_y_offset;
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wire [10-`X_BITS-1:0] rd_y_offset;
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wire [10-1:0] rd_x_remain;
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wire [10-1:0] rd_x_remain;
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wire [10-`X_BITS-1:0] rd_clr_remain;
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wire [10-`X_BITS-1:0] rd_clr_remain;
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wire rd_ch_end;
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wire rd_ch_end;
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wire rd_go_next_line;
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wire rd_go_next_line;
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wire rd_line_empty;
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wire rd_line_empty;
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wire rd_empty;
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wire rd_empty;
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wire [2-1:0] rd_align;
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wire [2-1:0] rd_align;
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//outputs of wr offsets
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//outputs of wr offsets
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wire [10-1:0] wr_x_offset;
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wire [10-1:0] wr_x_offset;
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wire [10-`X_BITS-1:0] wr_y_offset;
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wire [10-`X_BITS-1:0] wr_y_offset;
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wire [10-1:0] wr_x_remain;
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wire [10-1:0] wr_x_remain;
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wire [10-`X_BITS-1:0] wr_clr_remain;
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wire [10-`X_BITS-1:0] wr_clr_remain;
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wire wr_ch_end;
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wire wr_ch_end;
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wire wr_go_next_line;
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wire wr_go_next_line;
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wire wr_line_empty;
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wire wr_line_empty;
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wire wr_empty;
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wire wr_empty;
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wire [2-1:0] wr_align;
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wire [2-1:0] wr_align;
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wire wr_ch_end_pre;
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wire wr_ch_end_pre;
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reg wr_ch_end_reg;
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reg wr_ch_end_reg;
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//outputs of remain
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//outputs of remain
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wire [5:0] rd_gap;
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wire [5:0] rd_gap;
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wire [5:0] wr_fullness;
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wire [5:0] wr_fullness;
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//outputs of outs rd
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//outputs of outs rd
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wire rd_cmd_outs;
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wire rd_cmd_outs;
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wire rd_clr_outs;
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wire rd_clr_outs;
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wire [`OUT_BITS-1:0] rd_outs;
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wire [`OUT_BITS-1:0] rd_outs;
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wire rd_outs_empty;
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wire rd_outs_empty;
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wire outs_empty;
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wire outs_empty;
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wire rd_stall;
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wire rd_stall;
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wire timeout_rresp;
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wire timeout_rresp;
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//outputs of outs wr
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//outputs of outs wr
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wire wr_cmd_outs;
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wire wr_cmd_outs;
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wire wr_clr_outs;
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wire wr_clr_outs;
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wire [`OUT_BITS-1:0] wr_outs;
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wire [`OUT_BITS-1:0] wr_outs;
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wire wr_outs_empty;
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wire wr_outs_empty;
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wire wr_stall;
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wire wr_stall;
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wire wr_stall_pre;
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wire wr_stall_pre;
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wire timeout_wresp;
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wire timeout_wresp;
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//outputs of calc rd
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//outputs of calc rd
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wire rd_burst_last;
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wire rd_burst_last;
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wire [32-1:0] rd_burst_addr;
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wire [32-1:0] rd_burst_addr;
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wire [7-1:0] rd_burst_size;
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wire [7-1:0] rd_burst_size;
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wire rd_burst_ready;
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wire rd_burst_ready;
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wire rd_joint_ready;
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wire rd_joint_ready;
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wire rd_joint_flush;
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wire rd_joint_flush;
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wire joint_burst_req;
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wire joint_burst_req;
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//outputs of calc wr
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//outputs of calc wr
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wire wr_burst_last;
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wire wr_burst_last;
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wire [32-1:0] wr_burst_addr;
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wire [32-1:0] wr_burst_addr;
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wire [7-1:0] wr_burst_size;
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wire [7-1:0] wr_burst_size;
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wire wr_burst_ready;
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wire wr_burst_ready;
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wire wr_single;
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wire wr_single;
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wire wr_joint_ready;
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wire wr_joint_ready;
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wire wr_joint_flush;
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wire wr_joint_flush;
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wire joint_line_req;
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wire joint_line_req;
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//outputs of rd periph mux
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//outputs of rd periph mux
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wire [31:1] periph_rx_clr;
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wire [31:1] periph_rx_clr;
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wire rd_periph_ready;
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wire rd_periph_ready;
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//outputs of wr periph mux
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//outputs of wr periph mux
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wire [31:1] periph_tx_clr;
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wire [31:1] periph_tx_clr;
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wire wr_periph_ready;
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wire wr_periph_ready;
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//outputs of rd wait
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//outputs of rd wait
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wire rd_wait_ready;
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wire rd_wait_ready;
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//outputs of wr wait
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//outputs of wr wait
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wire wr_wait_ready;
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wire wr_wait_ready;
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//outputs of fifo_ctrl
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//outputs of fifo_ctrl
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wire fifo_wr_ready;
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wire fifo_wr_ready;
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wire fifo_overflow;
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wire fifo_overflow;
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wire fifo_underflow;
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wire fifo_underflow;
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wire rd_clr_block_pre;
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wire rd_clr_block_pre;
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wire rd_clr_block;
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wire rd_clr_block;
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wire rd_clr_valid;
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wire rd_clr_valid;
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wire wr_clr_block_pre;
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wire wr_clr_block_pre;
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wire wr_clr_block;
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wire wr_clr_block;
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wire wr_clr_valid;
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wire wr_clr_valid;
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wire wr_clr_mux;
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wire wr_clr_mux;
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wire rd_cmd_line_d;
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wire rd_cmd_line_d;
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wire rd_clr_stall;
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wire rd_clr_stall;
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wire wr_clr_stall;
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wire wr_clr_stall;
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wire allow_line_cmd;
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wire allow_line_cmd;
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wire load_cmd;
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wire load_cmd;
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wire [4:0] timeout_bus;
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wire [4:0] timeout_bus;
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wire joint_flush;
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wire joint_flush;
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wire page_cross;
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wire page_cross;
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reg joint_cross_reg;
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reg joint_cross_reg;
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wire joint_cross;
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wire joint_cross;
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reg rd_joint_not_in_prog;
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reg rd_joint_not_in_prog;
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reg wr_joint_not_in_prog;
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reg wr_joint_not_in_prog;
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wire joint_not_in_prog;
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wire joint_not_in_prog;
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reg rd_joint_in_prog;
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reg rd_joint_in_prog;
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reg wr_joint_in_prog;
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reg wr_joint_in_prog;
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wire joint_in_prog;
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wire joint_in_prog;
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wire rd_clr_outs_d_pre;
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wire rd_clr_outs_d_pre;
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wire rd_clr_outs_d;
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wire rd_clr_outs_d;
|
wire wr_clr_outs_d_pre;
|
wire wr_clr_outs_d_pre;
|
wire wr_clr_outs_d;
|
wire wr_clr_outs_d;
|
wire rd_clr_d;
|
wire rd_clr_d;
|
wire wr_clr_d;
|
wire wr_clr_d;
|
wire access_port0_mux;
|
wire access_port0_mux;
|
wire access_port1_mux;
|
wire access_port1_mux;
|
|
|
wire idle_pre;
|
wire idle_pre;
|
wire clk_en;
|
wire clk_en;
|
wire gclk;
|
wire gclk;
|
|
|
|
|
assign ch_active = ch_in_prog | load_in_prog;
|
assign ch_active = ch_in_prog | load_in_prog;
|
|
|
assign outs_empty = rd_outs_empty & wr_outs_empty;
|
assign outs_empty = rd_outs_empty & wr_outs_empty;
|
|
|
|
|
|
|
assign rd_clr_outs_d_pre = rd_clr_outs & (~rd_burst_start);
|
assign rd_clr_outs_d_pre = rd_clr_outs & (~rd_burst_start);
|
assign wr_clr_outs_d_pre = wr_clr_outs & (~wr_burst_start);
|
assign wr_clr_outs_d_pre = wr_clr_outs & (~wr_burst_start);
|
|
|
prgen_delay #(1) delay_rd_clr_outs (.clk(clk), .reset(reset), .din(rd_clr_outs_d_pre), .dout(rd_clr_outs_d));
|
prgen_delay #(1) delay_rd_clr_outs (.clk(clk), .reset(reset), .din(rd_clr_outs_d_pre), .dout(rd_clr_outs_d));
|
prgen_delay #(1) delay_wr_clr_outs (.clk(clk), .reset(reset), .din(wr_clr_outs_d_pre), .dout(wr_clr_outs_d));
|
prgen_delay #(1) delay_wr_clr_outs (.clk(clk), .reset(reset), .din(wr_clr_outs_d_pre), .dout(wr_clr_outs_d));
|
|
|
prgen_delay #(1) delay_rd_clr (.clk(clk), .reset(reset), .din(rd_clr), .dout(rd_clr_d));
|
prgen_delay #(1) delay_rd_clr (.clk(clk), .reset(reset), .din(rd_clr), .dout(rd_clr_d));
|
prgen_delay #(1) delay_wr_clr (.clk(clk), .reset(reset), .din(wr_clr), .dout(wr_clr_d));
|
prgen_delay #(1) delay_wr_clr (.clk(clk), .reset(reset), .din(wr_clr), .dout(wr_clr_d));
|
|
|
always @(posedge clk or posedge reset)
|
always @(posedge clk or posedge reset)
|
if (reset)
|
if (reset)
|
rd_joint_not_in_prog <= #1 1'b0;
|
rd_joint_not_in_prog <= #1 1'b0;
|
else if (ch_update)
|
else if (ch_update)
|
rd_joint_not_in_prog <= #1 1'b0;
|
rd_joint_not_in_prog <= #1 1'b0;
|
else if (rd_burst_start)
|
else if (rd_burst_start)
|
rd_joint_not_in_prog <= #1 (~joint_req);
|
rd_joint_not_in_prog <= #1 (~joint_req);
|
else if (rd_outs_empty & rd_clr_outs_d)
|
else if (rd_outs_empty & rd_clr_outs_d)
|
rd_joint_not_in_prog <= #1 1'b0;
|
rd_joint_not_in_prog <= #1 1'b0;
|
|
|
always @(posedge clk or posedge reset)
|
always @(posedge clk or posedge reset)
|
if (reset)
|
if (reset)
|
wr_joint_not_in_prog <= #1 1'b0;
|
wr_joint_not_in_prog <= #1 1'b0;
|
else if (ch_update)
|
else if (ch_update)
|
wr_joint_not_in_prog <= #1 1'b0;
|
wr_joint_not_in_prog <= #1 1'b0;
|
else if (wr_burst_start)
|
else if (wr_burst_start)
|
wr_joint_not_in_prog <= #1 (~joint_req);
|
wr_joint_not_in_prog <= #1 (~joint_req);
|
else if (wr_outs_empty & wr_clr_outs_d)
|
else if (wr_outs_empty & wr_clr_outs_d)
|
wr_joint_not_in_prog <= #1 1'b0;
|
wr_joint_not_in_prog <= #1 1'b0;
|
|
|
always @(posedge clk or posedge reset)
|
always @(posedge clk or posedge reset)
|
if (reset)
|
if (reset)
|
rd_joint_in_prog <= #1 1'b0;
|
rd_joint_in_prog <= #1 1'b0;
|
else if (ch_update)
|
else if (ch_update)
|
rd_joint_in_prog <= #1 1'b0;
|
rd_joint_in_prog <= #1 1'b0;
|
else if (rd_burst_start)
|
else if (rd_burst_start)
|
rd_joint_in_prog <= #1 joint_req;
|
rd_joint_in_prog <= #1 joint_req;
|
else if (rd_outs_empty & rd_clr_outs_d)
|
else if (rd_outs_empty & rd_clr_outs_d)
|
rd_joint_in_prog <= #1 1'b0;
|
rd_joint_in_prog <= #1 1'b0;
|
|
|
always @(posedge clk or posedge reset)
|
always @(posedge clk or posedge reset)
|
if (reset)
|
if (reset)
|
wr_joint_in_prog <= #1 1'b0;
|
wr_joint_in_prog <= #1 1'b0;
|
else if (ch_update)
|
else if (ch_update)
|
wr_joint_in_prog <= #1 1'b0;
|
wr_joint_in_prog <= #1 1'b0;
|
else if (wr_burst_start)
|
else if (wr_burst_start)
|
wr_joint_in_prog <= #1 joint_req;
|
wr_joint_in_prog <= #1 joint_req;
|
else if (wr_outs_empty & wr_clr_outs_d)
|
else if (wr_outs_empty & wr_clr_outs_d)
|
wr_joint_in_prog <= #1 1'b0;
|
wr_joint_in_prog <= #1 1'b0;
|
|
|
always @(posedge clk or posedge reset)
|
always @(posedge clk or posedge reset)
|
if (reset)
|
if (reset)
|
joint_cross_reg <= #1 1'b0;
|
joint_cross_reg <= #1 1'b0;
|
else if (ch_update)
|
else if (ch_update)
|
joint_cross_reg <= #1 1'b0;
|
joint_cross_reg <= #1 1'b0;
|
else if (page_cross & joint)
|
else if (page_cross & joint)
|
joint_cross_reg <= #1 1'b1;
|
joint_cross_reg <= #1 1'b1;
|
else if (joint_not_in_prog & outs_empty)
|
else if (joint_not_in_prog & outs_empty)
|
joint_cross_reg <= #1 1'b0;
|
joint_cross_reg <= #1 1'b0;
|
|
|
assign joint_cross = joint_cross_reg;
|
assign joint_cross = joint_cross_reg;
|
assign page_cross = rd_page_cross | wr_page_cross;
|
assign page_cross = rd_page_cross | wr_page_cross;
|
assign joint_in_prog = rd_joint_in_prog | wr_joint_in_prog;
|
assign joint_in_prog = rd_joint_in_prog | wr_joint_in_prog;
|
assign joint_not_in_prog = rd_joint_not_in_prog | wr_joint_not_in_prog;
|
assign joint_not_in_prog = rd_joint_not_in_prog | wr_joint_not_in_prog;
|
|
|
assign access_port0_mux = ((rd_port_num == 1'b0) | ((wr_port_num == 1'b0))) & 0;
|
assign access_port0_mux = ((rd_port_num == 1'b0) | ((wr_port_num == 1'b0))) & 0;
|
assign access_port1_mux = ((rd_port_num == 1'b1) | ((wr_port_num == 1'b1))) & 0;
|
assign access_port1_mux = ((rd_port_num == 1'b1) | ((wr_port_num == 1'b1))) & 0;
|
assign joint_mux_in_prog = joint_in_prog & (access_port0_mux | access_port1_mux);
|
assign joint_mux_in_prog = joint_in_prog & (access_port0_mux | access_port1_mux);
|
|
|
assign joint_req = joint & rd_joint_ready & wr_joint_ready & (~joint_cross) & (~load_req_in_prog);
|
assign joint_req = joint & rd_joint_ready & wr_joint_ready & (~joint_cross) & (~load_req_in_prog);
|
assign joint_flush = rd_joint_flush | wr_joint_flush;
|
assign joint_flush = rd_joint_flush | wr_joint_flush;
|
|
|
|
|
assign rd_clr_block = 1'b1;
|
assign rd_clr_block = 1'b1;
|
assign wr_clr_block = 1'b1;
|
assign wr_clr_block = 1'b1;
|
assign wr_clr_mux = wr_clr;
|
assign wr_clr_mux = wr_clr;
|
assign rd_clr_stall = 1'b0;
|
assign rd_clr_stall = 1'b0;
|
assign wr_clr_stall = 1'b0;
|
assign wr_clr_stall = 1'b0;
|
assign allow_line_cmd = 1'b0;
|
assign allow_line_cmd = 1'b0;
|
assign rd_line_cmd = 1'b0;
|
assign rd_line_cmd = 1'b0;
|
assign wr_line_cmd = 1'b0;
|
assign wr_line_cmd = 1'b0;
|
|
|
assign rd_clr_valid = rd_clr_block & (~ch_retry_wait);
|
assign rd_clr_valid = rd_clr_block & (~ch_retry_wait);
|
assign wr_clr_valid = wr_clr_block & (~ch_retry_wait);
|
assign wr_clr_valid = wr_clr_block & (~ch_retry_wait);
|
|
|
assign rd_ready = (~rd_stall) & (~rd_clr_stall) &
|
assign rd_ready = (~rd_stall) & (~rd_clr_stall) &
|
ch_rd_active & (rd_periph_ready | load_req_in_prog) &
|
ch_rd_active & (rd_periph_ready | load_req_in_prog) &
|
rd_wait_ready & rd_burst_ready;
|
rd_wait_ready & rd_burst_ready;
|
|
|
|
|
assign wr_ready = (~wr_stall) & (~wr_clr_stall) &
|
assign wr_ready = (~wr_stall) & (~wr_clr_stall) &
|
ch_wr_active & wr_periph_ready &
|
ch_wr_active & wr_periph_ready &
|
wr_wait_ready & wr_burst_ready;
|
wr_wait_ready & wr_burst_ready;
|
|
|
assign wr_last_cmd = wr_empty;
|
assign wr_last_cmd = wr_empty;
|
|
|
assign load_cmd = load_req_in_prog & rd_burst_start;
|
assign load_cmd = load_req_in_prog & rd_burst_start;
|
|
|
assign rd_cmd_outs = rd_burst_start | rd_cmd_split;
|
assign rd_cmd_outs = rd_burst_start | rd_cmd_split;
|
assign wr_cmd_outs = wr_burst_start | wr_cmd_split;
|
assign wr_cmd_outs = wr_burst_start | wr_cmd_split;
|
|
|
assign rd_clr_outs = rd_clr | rd_clr_load;
|
assign rd_clr_outs = rd_clr | rd_clr_load;
|
assign wr_clr_outs = wr_clr;
|
assign wr_clr_outs = wr_clr;
|
|
|
|
|
assign timeout_bus = {
|
assign timeout_bus = {
|
timeout_aw,
|
timeout_aw,
|
timeout_w,
|
timeout_w,
|
{timeout_wresp & (~timeout_aw)},
|
{timeout_wresp & (~timeout_aw)},
|
timeout_ar,
|
timeout_ar,
|
{timeout_rresp & (~timeout_ar)}
|
{timeout_rresp & (~timeout_ar)}
|
};
|
};
|
|
|
|
|
assign clk_en = ch_active | ch_update | (~outs_empty) | (~rd_wait_ready) | (~wr_wait_ready);
|
assign clk_en = ch_active | ch_update | (~outs_empty) | (~rd_wait_ready) | (~wr_wait_ready);
|
|
|
assign idle_pre = !clk_en;
|
assign idle_pre = !clk_en;
|
prgen_delay #(1) delay_idle (.clk(clk), .reset(reset), .din(idle_pre), .dout(idle));
|
prgen_delay #(1) delay_idle (.clk(clk), .reset(reset), .din(idle_pre), .dout(idle));
|
|
|
assign gclk = clk;
|
assign gclk = clk;
|
|
|
|
|
dma_axi32_core0_ch_reg
|
dma_axi32_core0_ch_reg
|
dma_axi32_ch_reg (
|
dma_axi32_ch_reg (
|
.clk(pclk),
|
.clk(pclk),
|
.clken(clken),
|
.clken(clken),
|
.pclken(pclken),
|
.pclken(pclken),
|
.reset(reset),
|
.reset(reset),
|
.psel(psel),
|
.psel(psel),
|
.penable(penable),
|
.penable(penable),
|
.paddr(paddr),
|
.paddr(paddr),
|
.pwrite(pwrite),
|
.pwrite(pwrite),
|
.pwdata(pwdata),
|
.pwdata(pwdata),
|
.prdata(prdata),
|
.prdata(prdata),
|
.pslverr(pslverr),
|
.pslverr(pslverr),
|
|
|
.timeout_bus(timeout_bus),
|
.timeout_bus(timeout_bus),
|
.wdt_timeout(wdt_timeout),
|
.wdt_timeout(wdt_timeout),
|
|
|
.ch_start(ch_start),
|
.ch_start(ch_start),
|
.load_wr(load_wr),
|
.load_wr(load_wr),
|
.load_wr_cycle(load_wr_cycle),
|
.load_wr_cycle(load_wr_cycle),
|
.load_wdata(load_wdata),
|
.load_wdata(load_wdata),
|
.load_in_prog(load_in_prog),
|
.load_in_prog(load_in_prog),
|
.load_req_in_prog(load_req_in_prog),
|
.load_req_in_prog(load_req_in_prog),
|
.rd_ch_end(rd_ch_end),
|
.rd_ch_end(rd_ch_end),
|
.wr_ch_end(wr_ch_end),
|
.wr_ch_end(wr_ch_end),
|
.wr_clr_last(wr_clr_last),
|
.wr_clr_last(wr_clr_last),
|
.rd_slverr(rd_slverr),
|
.rd_slverr(rd_slverr),
|
.rd_decerr(rd_decerr),
|
.rd_decerr(rd_decerr),
|
.wr_slverr(wr_slverr),
|
.wr_slverr(wr_slverr),
|
.wr_decerr(wr_decerr),
|
.wr_decerr(wr_decerr),
|
.int_all_proc(int_all_proc),
|
.int_all_proc(int_all_proc),
|
.ch_rd_active(ch_rd_active),
|
.ch_rd_active(ch_rd_active),
|
.ch_wr_active(ch_wr_active),
|
.ch_wr_active(ch_wr_active),
|
.ch_in_prog(ch_in_prog),
|
.ch_in_prog(ch_in_prog),
|
.wr_outstanding(wr_outstanding),
|
.wr_outstanding(wr_outstanding),
|
.rd_outstanding(rd_outstanding),
|
.rd_outstanding(rd_outstanding),
|
.ch_retry_wait(ch_retry_wait),
|
.ch_retry_wait(ch_retry_wait),
|
|
|
.joint_mode(joint_mode),
|
.joint_mode(joint_mode),
|
.joint_remote(joint_remote),
|
.joint_remote(joint_remote),
|
.joint(joint),
|
.joint(joint),
|
.joint_cross(joint_cross),
|
.joint_cross(joint_cross),
|
.page_cross(page_cross),
|
.page_cross(page_cross),
|
.joint_flush(joint_flush),
|
.joint_flush(joint_flush),
|
|
|
.rd_x_offset(rd_x_offset),
|
.rd_x_offset(rd_x_offset),
|
.rd_y_offset(rd_y_offset),
|
.rd_y_offset(rd_y_offset),
|
.wr_x_offset(wr_x_offset),
|
.wr_x_offset(wr_x_offset),
|
.wr_y_offset(wr_y_offset),
|
.wr_y_offset(wr_y_offset),
|
.rd_gap(rd_gap),
|
.rd_gap(rd_gap),
|
.wr_fullness(wr_fullness),
|
.wr_fullness(wr_fullness),
|
.fifo_overflow(fifo_overflow),
|
.fifo_overflow(fifo_overflow),
|
.fifo_underflow(fifo_underflow),
|
.fifo_underflow(fifo_underflow),
|
|
|
.load_cmd(load_cmd),
|
.load_cmd(load_cmd),
|
.load_addr(load_addr),
|
.load_addr(load_addr),
|
|
|
.ch_update(ch_update),
|
.ch_update(ch_update),
|
.rd_start_addr(rd_start_addr),
|
.rd_start_addr(rd_start_addr),
|
.wr_start_addr(wr_start_addr),
|
.wr_start_addr(wr_start_addr),
|
.x_size(x_size),
|
.x_size(x_size),
|
.y_size(y_size),
|
.y_size(y_size),
|
|
|
.rd_burst_max_size(rd_burst_max_size),
|
.rd_burst_max_size(rd_burst_max_size),
|
.wr_burst_max_size(wr_burst_max_size),
|
.wr_burst_max_size(wr_burst_max_size),
|
.rd_periph_delay(rd_periph_delay),
|
.rd_periph_delay(rd_periph_delay),
|
.wr_periph_delay(wr_periph_delay),
|
.wr_periph_delay(wr_periph_delay),
|
.rd_periph_block(rd_periph_block),
|
.rd_periph_block(rd_periph_block),
|
.wr_periph_block(wr_periph_block),
|
.wr_periph_block(wr_periph_block),
|
.rd_tokens(rd_tokens),
|
.rd_tokens(rd_tokens),
|
.wr_tokens(wr_tokens),
|
.wr_tokens(wr_tokens),
|
.end_swap(end_swap),
|
.end_swap(end_swap),
|
.rd_port_num(rd_port_num),
|
.rd_port_num(rd_port_num),
|
.wr_port_num(wr_port_num),
|
.wr_port_num(wr_port_num),
|
.rd_outs_max(rd_outs_max),
|
.rd_outs_max(rd_outs_max),
|
.wr_outs_max(wr_outs_max),
|
.wr_outs_max(wr_outs_max),
|
.rd_outs(rd_outs),
|
.rd_outs(rd_outs),
|
.wr_outs(wr_outs),
|
.wr_outs(wr_outs),
|
.outs_empty(outs_empty),
|
.outs_empty(outs_empty),
|
.rd_wait_limit(rd_wait_limit),
|
.rd_wait_limit(rd_wait_limit),
|
.wr_wait_limit(wr_wait_limit),
|
.wr_wait_limit(wr_wait_limit),
|
.rd_periph_num(rd_periph_num),
|
.rd_periph_num(rd_periph_num),
|
.wr_periph_num(wr_periph_num),
|
.wr_periph_num(wr_periph_num),
|
.rd_incr(rd_incr),
|
.rd_incr(rd_incr),
|
.wr_incr(wr_incr),
|
.wr_incr(wr_incr),
|
.block(block),
|
.block(block),
|
.allow_line_cmd(allow_line_cmd),
|
.allow_line_cmd(allow_line_cmd),
|
.frame_width(frame_width),
|
.frame_width(frame_width),
|
.width_align(width_align)
|
.width_align(width_align)
|
);
|
);
|
|
|
|
|
dma_axi32_core0_ch_offsets
|
dma_axi32_core0_ch_offsets
|
dma_axi32_ch_offsets_rd (
|
dma_axi32_ch_offsets_rd (
|
.clk(gclk),
|
.clk(gclk),
|
.reset(reset),
|
.reset(reset),
|
.ch_update(ch_update),
|
.ch_update(ch_update),
|
.burst_start(rd_burst_start),
|
.burst_start(rd_burst_start),
|
.burst_last(rd_burst_last),
|
.burst_last(rd_burst_last),
|
.burst_size(rd_burst_size),
|
.burst_size(rd_burst_size),
|
.load_req_in_prog(load_req_in_prog),
|
.load_req_in_prog(load_req_in_prog),
|
.x_size(x_size),
|
.x_size(x_size),
|
.y_size(y_size),
|
.y_size(y_size),
|
.x_offset(rd_x_offset),
|
.x_offset(rd_x_offset),
|
.y_offset(rd_y_offset),
|
.y_offset(rd_y_offset),
|
.x_remain(rd_x_remain),
|
.x_remain(rd_x_remain),
|
.clr_remain(rd_clr_remain),
|
.clr_remain(rd_clr_remain),
|
.ch_end(rd_ch_end),
|
.ch_end(rd_ch_end),
|
.go_next_line(rd_go_next_line),
|
.go_next_line(rd_go_next_line),
|
.incr(rd_incr),
|
.incr(rd_incr),
|
.clr_line(rd_clr_line),
|
.clr_line(rd_clr_line),
|
.line_empty(rd_line_empty),
|
.line_empty(rd_line_empty),
|
.empty(rd_empty),
|
.empty(rd_empty),
|
.start_align(rd_start_addr[2-1:0]),
|
.start_align(rd_start_addr[2-1:0]),
|
.width_align(width_align),
|
.width_align(width_align),
|
.align(wr_align) //rd address writes to fifo
|
.align(wr_align) //rd address writes to fifo
|
);
|
);
|
|
|
dma_axi32_core0_ch_offsets
|
dma_axi32_core0_ch_offsets
|
dma_axi32_ch_offsets_wr (
|
dma_axi32_ch_offsets_wr (
|
.clk(gclk),
|
.clk(gclk),
|
.reset(reset),
|
.reset(reset),
|
.ch_update(ch_update),
|
.ch_update(ch_update),
|
.burst_start(wr_burst_start),
|
.burst_start(wr_burst_start),
|
.burst_last(wr_burst_last),
|
.burst_last(wr_burst_last),
|
.burst_size(wr_burst_size),
|
.burst_size(wr_burst_size),
|
.load_req_in_prog(1'b0),
|
.load_req_in_prog(1'b0),
|
.x_size(x_size),
|
.x_size(x_size),
|
.y_size(y_size),
|
.y_size(y_size),
|
.x_offset(wr_x_offset),
|
.x_offset(wr_x_offset),
|
.y_offset(wr_y_offset),
|
.y_offset(wr_y_offset),
|
.x_remain(wr_x_remain),
|
.x_remain(wr_x_remain),
|
.clr_remain(wr_clr_remain),
|
.clr_remain(wr_clr_remain),
|
.ch_end(wr_ch_end),
|
.ch_end(wr_ch_end),
|
.go_next_line(wr_go_next_line),
|
.go_next_line(wr_go_next_line),
|
.incr(wr_incr),
|
.incr(wr_incr),
|
.clr_line(wr_clr_line),
|
.clr_line(wr_clr_line),
|
.line_empty(wr_line_empty),
|
.line_empty(wr_line_empty),
|
.empty(wr_empty),
|
.empty(wr_empty),
|
.start_align(wr_start_addr[2-1:0]),
|
.start_align(wr_start_addr[2-1:0]),
|
.width_align(width_align),
|
.width_align(width_align),
|
.align(rd_align) //wr address reads from fifo
|
.align(rd_align) //wr address reads from fifo
|
);
|
);
|
|
|
|
|
dma_axi32_core0_ch_remain
|
dma_axi32_core0_ch_remain
|
dma_axi32_ch_remain (
|
dma_axi32_ch_remain (
|
.clk(gclk),
|
.clk(gclk),
|
.reset(reset),
|
.reset(reset),
|
.ch_update(ch_update),
|
.ch_update(ch_update),
|
.wr_outstanding(wr_outstanding),
|
.wr_outstanding(wr_outstanding),
|
.rd_outstanding(rd_outstanding),
|
.rd_outstanding(rd_outstanding),
|
.load_req_in_prog(load_req_in_prog),
|
.load_req_in_prog(load_req_in_prog),
|
.rd_line_cmd(rd_line_cmd),
|
.rd_line_cmd(rd_line_cmd),
|
.rd_burst_start(rd_burst_start),
|
.rd_burst_start(rd_burst_start),
|
.rd_burst_size(rd_burst_size),
|
.rd_burst_size(rd_burst_size),
|
.rd_transfer(rd_transfer),
|
.rd_transfer(rd_transfer),
|
.rd_transfer_size(rd_transfer_size),
|
.rd_transfer_size(rd_transfer_size),
|
.wr_clr_line(wr_clr_line),
|
.wr_clr_line(wr_clr_line),
|
.wr_burst_start(wr_burst_start),
|
.wr_burst_start(wr_burst_start),
|
.wr_burst_size(wr_burst_size),
|
.wr_burst_size(wr_burst_size),
|
.wr_transfer(wr_transfer),
|
.wr_transfer(wr_transfer),
|
.wr_transfer_size(wr_transfer_size),
|
.wr_transfer_size(wr_transfer_size),
|
.rd_gap(rd_gap),
|
.rd_gap(rd_gap),
|
.wr_fullness(wr_fullness)
|
.wr_fullness(wr_fullness)
|
);
|
);
|
|
|
|
|
dma_axi32_core0_ch_outs dma_axi32_ch_outs_rd(
|
dma_axi32_core0_ch_outs dma_axi32_ch_outs_rd(
|
.clk(gclk),
|
.clk(gclk),
|
.reset(reset),
|
.reset(reset),
|
.cmd(rd_cmd_outs),
|
.cmd(rd_cmd_outs),
|
.clr(rd_clr_outs),
|
.clr(rd_clr_outs),
|
.outs_max(rd_outs_max),
|
.outs_max(rd_outs_max),
|
.outs(rd_outs),
|
.outs(rd_outs),
|
.outs_empty(rd_outs_empty),
|
.outs_empty(rd_outs_empty),
|
.stall(rd_stall),
|
.stall(rd_stall),
|
.timeout(timeout_rresp)
|
.timeout(timeout_rresp)
|
);
|
);
|
|
|
dma_axi32_core0_ch_outs dma_axi32_ch_outs_wr(
|
dma_axi32_core0_ch_outs dma_axi32_ch_outs_wr(
|
.clk(gclk),
|
.clk(gclk),
|
.reset(reset),
|
.reset(reset),
|
.cmd(wr_cmd_outs),
|
.cmd(wr_cmd_outs),
|
.clr(wr_clr_outs),
|
.clr(wr_clr_outs),
|
.outs_max(wr_outs_max),
|
.outs_max(wr_outs_max),
|
.outs(wr_outs),
|
.outs(wr_outs),
|
.outs_empty(wr_outs_empty),
|
.outs_empty(wr_outs_empty),
|
.stall(wr_stall_pre),
|
.stall(wr_stall_pre),
|
.timeout(timeout_wresp)
|
.timeout(timeout_wresp)
|
);
|
);
|
|
|
assign wr_stall = wr_stall_pre & (~joint_req);
|
assign wr_stall = wr_stall_pre & (~joint_req);
|
|
|
|
|
|
|
dma_axi32_core0_ch_calc #(.READ(1))
|
dma_axi32_core0_ch_calc #(.READ(1))
|
dma_axi32_ch_calc_rd (
|
dma_axi32_ch_calc_rd (
|
.clk(gclk),
|
.clk(gclk),
|
.reset(reset),
|
.reset(reset),
|
.wr_cmd_pending(1'b0),
|
.wr_cmd_pending(1'b0),
|
.outs_empty(outs_empty),
|
.outs_empty(outs_empty),
|
.load_in_prog(load_in_prog),
|
.load_in_prog(load_in_prog),
|
.load_req_in_prog(load_req_in_prog),
|
.load_req_in_prog(load_req_in_prog),
|
.load_addr(load_addr),
|
.load_addr(load_addr),
|
.ch_update(ch_update),
|
.ch_update(ch_update),
|
.ch_end(rd_ch_end),
|
.ch_end(rd_ch_end),
|
.ch_end_flush(1'b0),
|
.ch_end_flush(1'b0),
|
.go_next_line(rd_go_next_line),
|
.go_next_line(rd_go_next_line),
|
.burst_start(rd_burst_start),
|
.burst_start(rd_burst_start),
|
.burst_last(rd_burst_last),
|
.burst_last(rd_burst_last),
|
.burst_max_size(rd_burst_max_size),
|
.burst_max_size(rd_burst_max_size),
|
.start_addr(rd_start_addr),
|
.start_addr(rd_start_addr),
|
.incr(rd_incr),
|
.incr(rd_incr),
|
.frame_width(frame_width),
|
.frame_width(frame_width),
|
.x_size(x_size[`X_BITS-1:0]),
|
.x_size(x_size[`X_BITS-1:0]),
|
.x_remain(rd_x_remain),
|
.x_remain(rd_x_remain),
|
.fifo_remain(rd_gap),
|
.fifo_remain(rd_gap),
|
.fifo_wr_ready(fifo_wr_ready),
|
.fifo_wr_ready(fifo_wr_ready),
|
.burst_addr(rd_burst_addr),
|
.burst_addr(rd_burst_addr),
|
.burst_size(rd_burst_size),
|
.burst_size(rd_burst_size),
|
.burst_ready(rd_burst_ready),
|
.burst_ready(rd_burst_ready),
|
.single(),
|
.single(),
|
.joint_ready_out(rd_joint_ready),
|
.joint_ready_out(rd_joint_ready),
|
.joint_ready_in(wr_joint_ready),
|
.joint_ready_in(wr_joint_ready),
|
.joint_line_req_in(joint_line_req),
|
.joint_line_req_in(joint_line_req),
|
.joint_line_req_out(),
|
.joint_line_req_out(),
|
.joint_burst_req_in(1'b0),
|
.joint_burst_req_in(1'b0),
|
.joint_burst_req_out(joint_burst_req),
|
.joint_burst_req_out(joint_burst_req),
|
.joint_line_req_clr(wr_clr_d),
|
.joint_line_req_clr(wr_clr_d),
|
.joint(joint),
|
.joint(joint),
|
.page_cross(rd_page_cross),
|
.page_cross(rd_page_cross),
|
.joint_cross(joint_cross),
|
.joint_cross(joint_cross),
|
.joint_flush(rd_joint_flush),
|
.joint_flush(rd_joint_flush),
|
.joint_flush_in(joint_flush)
|
.joint_flush_in(joint_flush)
|
);
|
);
|
|
|
|
|
dma_axi32_core0_ch_calc #(.READ(0))
|
dma_axi32_core0_ch_calc #(.READ(0))
|
dma_axi32_ch_calc_wr (
|
dma_axi32_ch_calc_wr (
|
.clk(gclk),
|
.clk(gclk),
|
.reset(reset),
|
.reset(reset),
|
.wr_cmd_pending(wr_cmd_pending),
|
.wr_cmd_pending(wr_cmd_pending),
|
.outs_empty(outs_empty),
|
.outs_empty(outs_empty),
|
.load_in_prog(load_in_prog),
|
.load_in_prog(load_in_prog),
|
.load_req_in_prog(1'b0),
|
.load_req_in_prog(1'b0),
|
.load_addr({32{1'b0}}),
|
.load_addr({32{1'b0}}),
|
.ch_update(ch_update),
|
.ch_update(ch_update),
|
.ch_end(wr_ch_end),
|
.ch_end(wr_ch_end),
|
.ch_end_flush(rd_ch_end),
|
.ch_end_flush(rd_ch_end),
|
.go_next_line(wr_go_next_line),
|
.go_next_line(wr_go_next_line),
|
.burst_start(wr_burst_start),
|
.burst_start(wr_burst_start),
|
.burst_last(wr_burst_last),
|
.burst_last(wr_burst_last),
|
.burst_max_size(wr_burst_max_size),
|
.burst_max_size(wr_burst_max_size),
|
.start_addr(wr_start_addr),
|
.start_addr(wr_start_addr),
|
.incr(wr_incr),
|
.incr(wr_incr),
|
.frame_width(frame_width),
|
.frame_width(frame_width),
|
.x_size(x_size[`X_BITS-1:0]),
|
.x_size(x_size[`X_BITS-1:0]),
|
.x_remain(wr_x_remain),
|
.x_remain(wr_x_remain),
|
.fifo_wr_ready(1'b0),
|
.fifo_wr_ready(1'b0),
|
.fifo_remain(wr_fullness),
|
.fifo_remain(wr_fullness),
|
.burst_addr(wr_burst_addr),
|
.burst_addr(wr_burst_addr),
|
.burst_size(wr_burst_size),
|
.burst_size(wr_burst_size),
|
.burst_ready(wr_burst_ready),
|
.burst_ready(wr_burst_ready),
|
.single(wr_single),
|
.single(wr_single),
|
.joint_ready_out(wr_joint_ready),
|
.joint_ready_out(wr_joint_ready),
|
.joint_ready_in(rd_joint_ready),
|
.joint_ready_in(rd_joint_ready),
|
.joint_line_req_in(1'b0),
|
.joint_line_req_in(1'b0),
|
.joint_line_req_out(joint_line_req),
|
.joint_line_req_out(joint_line_req),
|
.joint_burst_req_in(joint_burst_req),
|
.joint_burst_req_in(joint_burst_req),
|
.joint_burst_req_out(),
|
.joint_burst_req_out(),
|
.joint_line_req_clr(rd_clr_d),
|
.joint_line_req_clr(rd_clr_d),
|
.joint(joint),
|
.joint(joint),
|
.page_cross(wr_page_cross),
|
.page_cross(wr_page_cross),
|
.joint_cross(joint_cross),
|
.joint_cross(joint_cross),
|
.joint_flush(wr_joint_flush),
|
.joint_flush(wr_joint_flush),
|
.joint_flush_in(joint_flush)
|
.joint_flush_in(joint_flush)
|
);
|
);
|
|
|
|
|
assign rd_wait_ready = 1'b1;
|
assign rd_wait_ready = 1'b1;
|
assign wr_wait_ready = 1'b1;
|
assign wr_wait_ready = 1'b1;
|
|
|
|
|
|
|
dma_axi32_core0_ch_periph_mux dma_axi32_ch_periph_mux_rd(
|
dma_axi32_core0_ch_periph_mux dma_axi32_ch_periph_mux_rd(
|
.clk(gclk),
|
.clk(gclk),
|
.reset(reset),
|
.reset(reset),
|
.clken(clken),
|
.clken(clken),
|
.periph_req(periph_rx_req),
|
.periph_req(periph_rx_req),
|
.periph_clr(periph_rx_clr),
|
.periph_clr(periph_rx_clr),
|
.periph_ready(rd_periph_ready),
|
.periph_ready(rd_periph_ready),
|
.periph_num(rd_periph_num),
|
.periph_num(rd_periph_num),
|
.clr_valid(rd_clr_valid),
|
.clr_valid(rd_clr_valid),
|
.clr(rd_clr)
|
.clr(rd_clr)
|
);
|
);
|
|
|
|
|
dma_axi32_core0_ch_periph_mux dma_axi32_ch_periph_mux_wr(
|
dma_axi32_core0_ch_periph_mux dma_axi32_ch_periph_mux_wr(
|
.clk(gclk),
|
.clk(gclk),
|
.reset(reset),
|
.reset(reset),
|
.clken(clken),
|
.clken(clken),
|
.periph_req(periph_tx_req),
|
.periph_req(periph_tx_req),
|
.periph_clr(periph_tx_clr),
|
.periph_clr(periph_tx_clr),
|
.periph_ready(wr_periph_ready),
|
.periph_ready(wr_periph_ready),
|
.periph_num(wr_periph_num),
|
.periph_num(wr_periph_num),
|
.clr_valid(wr_clr_valid),
|
.clr_valid(wr_clr_valid),
|
.clr(wr_clr_mux)
|
.clr(wr_clr_mux)
|
);
|
);
|
|
|
|
|
|
|
dma_axi32_core0_ch_fifo_ctrl
|
dma_axi32_core0_ch_fifo_ctrl
|
dma_axi32_ch_fifo_ctrl (
|
dma_axi32_ch_fifo_ctrl (
|
.clk(clk),
|
.clk(clk),
|
.reset(reset),
|
.reset(reset),
|
.end_swap(end_swap),
|
.end_swap(end_swap),
|
.joint_in_prog(joint_in_prog),
|
.joint_in_prog(joint_in_prog),
|
.wr_outstanding(wr_outstanding),
|
.wr_outstanding(wr_outstanding),
|
.ch_update(ch_update),
|
.ch_update(ch_update),
|
.fifo_wr(fifo_wr),
|
.fifo_wr(fifo_wr),
|
.fifo_wdata(fifo_wdata),
|
.fifo_wdata(fifo_wdata),
|
.fifo_wsize(fifo_wsize),
|
.fifo_wsize(fifo_wsize),
|
.wr_align(wr_align),
|
.wr_align(wr_align),
|
.wr_single(wr_single),
|
.wr_single(wr_single),
|
.rd_incr(rd_incr),
|
.rd_incr(rd_incr),
|
.fifo_rd(fifo_rd),
|
.fifo_rd(fifo_rd),
|
.fifo_rsize(fifo_rsize),
|
.fifo_rsize(fifo_rsize),
|
.rd_align(rd_align),
|
.rd_align(rd_align),
|
.wr_incr(wr_incr),
|
.wr_incr(wr_incr),
|
.wr_burst_size(wr_burst_size),
|
.wr_burst_size(wr_burst_size),
|
.rd_clr_line(rd_clr_line),
|
.rd_clr_line(rd_clr_line),
|
.wr_clr_line(wr_clr_line),
|
.wr_clr_line(wr_clr_line),
|
.wr_next_size(wr_next_size),
|
.wr_next_size(wr_next_size),
|
|
|
.fifo_rd_valid(fifo_rd_valid),
|
.fifo_rd_valid(fifo_rd_valid),
|
.fifo_rdata(fifo_rdata),
|
.fifo_rdata(fifo_rdata),
|
.fifo_wr_ready(fifo_wr_ready),
|
.fifo_wr_ready(fifo_wr_ready),
|
.fifo_overflow(fifo_overflow),
|
.fifo_overflow(fifo_overflow),
|
.fifo_underflow(fifo_underflow)
|
.fifo_underflow(fifo_underflow)
|
);
|
);
|
|
|
|
|
|
|
|
|
|
|
endmodule
|
endmodule
|
|
|
|
|
|
|