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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Author: Eyal Hochberg ////
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//// eyal@provartec.com ////
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//// ////
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//// Downloaded from: http://www.opencores.org ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2010 Provartec LTD ////
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//// www.provartec.com ////
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//// info@provartec.com ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation.////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more////
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//// details. http://www.gnu.org/licenses/lgpl.html ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//---------------------------------------------------------
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//---------------------------------------------------------
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//-- File generated by RobustVerilog parser
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//-- File generated by RobustVerilog parser
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//-- Version: 1.0
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//-- Version: 1.0
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//-- Invoked Fri Mar 25 23:34:54 2011
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//-- Invoked Fri Mar 25 23:34:54 2011
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//--
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//--
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//-- Source file: dma_ch_calc_joint.v
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//-- Source file: dma_ch_calc_joint.v
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//---------------------------------------------------------
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//---------------------------------------------------------
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module dma_axi32_core0_ch_calc_joint(clk,reset,joint_update,ch_end,ch_end_flush,joint_line_req_clr,wr_cmd_pending,burst_size_pre2,burst_max_size,fifo_not_ready,outs_empty,x_remain,fifo_wr_ready,fifo_remain,joint,page_cross,joint_cross,joint_ready_in,joint_ready_out,joint_line_req,joint_burst_req,joint_wait,joint_flush,joint_flush_in,joint_buffer_small);
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module dma_axi32_core0_ch_calc_joint(clk,reset,joint_update,ch_end,ch_end_flush,joint_line_req_clr,wr_cmd_pending,burst_size_pre2,burst_max_size,fifo_not_ready,outs_empty,x_remain,fifo_wr_ready,fifo_remain,joint,page_cross,joint_cross,joint_ready_in,joint_ready_out,joint_line_req,joint_burst_req,joint_wait,joint_flush,joint_flush_in,joint_buffer_small);
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parameter READ = 0;
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parameter READ = 0;
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parameter WRITE = !READ;
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parameter WRITE = !READ;
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input clk;
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input clk;
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input reset;
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input reset;
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input joint_update;
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input joint_update;
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input ch_end;
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input ch_end;
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input ch_end_flush;
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input ch_end_flush;
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input joint_line_req_clr;
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input joint_line_req_clr;
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input wr_cmd_pending;
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input wr_cmd_pending;
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input [7-1:0] burst_size_pre2;
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input [7-1:0] burst_size_pre2;
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input [7-1:0] burst_max_size;
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input [7-1:0] burst_max_size;
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input fifo_not_ready;
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input fifo_not_ready;
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input outs_empty;
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input outs_empty;
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input [10-1:0] x_remain;
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input [10-1:0] x_remain;
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input fifo_wr_ready;
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input fifo_wr_ready;
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input [5:0] fifo_remain;
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input [5:0] fifo_remain;
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input joint;
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input joint;
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input page_cross;
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input page_cross;
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input joint_cross;
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input joint_cross;
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input joint_ready_in;
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input joint_ready_in;
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output joint_ready_out;
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output joint_ready_out;
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output joint_line_req;
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output joint_line_req;
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output joint_burst_req;
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output joint_burst_req;
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output joint_wait;
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output joint_wait;
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output joint_flush;
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output joint_flush;
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input joint_flush_in;
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input joint_flush_in;
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output joint_buffer_small;
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output joint_buffer_small;
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parameter IDLE = 3'd0;
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parameter IDLE = 3'd0;
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parameter REQ_LINE = 3'd1;
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parameter REQ_LINE = 3'd1;
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parameter READY_OUT = 3'd2;
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parameter READY_OUT = 3'd2;
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parameter READY = 3'd3;
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parameter READY = 3'd3;
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parameter CROSS = 3'd4;
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parameter CROSS = 3'd4;
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parameter BURST_REQ = 3'd5;
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parameter BURST_REQ = 3'd5;
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parameter RECHK = 3'd6;
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parameter RECHK = 3'd6;
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parameter FLUSH = 3'd7;
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parameter FLUSH = 3'd7;
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reg [2:0] ps;
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reg [2:0] ps;
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reg [2:0] ns;
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reg [2:0] ns;
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wire joint_ready_out_pre;
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wire joint_ready_out_pre;
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reg joint_ready_out;
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reg joint_ready_out;
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reg joint_line_req;
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reg joint_line_req;
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reg joint_burst_req;
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reg joint_burst_req;
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reg joint_flush;
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reg joint_flush;
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reg joint_wait;
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reg joint_wait;
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wire joint_buffer_small;
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wire joint_buffer_small;
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assign joint_ready_out_pre = joint & (burst_size_pre2 == burst_max_size) & (|burst_max_size) &
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assign joint_ready_out_pre = joint & (burst_size_pre2 == burst_max_size) & (|burst_max_size) &
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(~joint_line_req) & (~joint_burst_req);
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(~joint_line_req) & (~joint_burst_req);
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assign joint_buffer_small = (burst_max_size > x_remain) | (x_remain < 'd8);
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assign joint_buffer_small = (burst_max_size > x_remain) | (x_remain < 'd8);
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always @(posedge clk or posedge reset)
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always @(posedge clk or posedge reset)
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if (reset)
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if (reset)
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joint_ready_out <= #1 1'b0;
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joint_ready_out <= #1 1'b0;
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else if ((page_cross | ch_end_flush | joint_flush | joint_wait) & (~ch_end))
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else if ((page_cross | ch_end_flush | joint_flush | joint_wait) & (~ch_end))
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joint_ready_out <= #1 1'b0;
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joint_ready_out <= #1 1'b0;
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else if ((~ch_end) & (~wr_cmd_pending))
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else if ((~ch_end) & (~wr_cmd_pending))
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joint_ready_out <= #1 joint_ready_out_pre;
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joint_ready_out <= #1 joint_ready_out_pre;
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always @(/*AUTOSENSE*/ch_end_flush or fifo_not_ready or fifo_remain
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always @(/*AUTOSENSE*/ch_end_flush or fifo_not_ready or fifo_remain
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or fifo_wr_ready or joint_buffer_small or joint_cross
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or fifo_wr_ready or joint_buffer_small or joint_cross
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or joint_flush_in or joint_line_req_clr or joint_ready_in
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or joint_flush_in or joint_line_req_clr or joint_ready_in
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or joint_ready_out or outs_empty or page_cross or ps)
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or joint_ready_out or outs_empty or page_cross or ps)
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begin
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begin
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ns = IDLE;
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ns = IDLE;
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joint_line_req = 1'b0;
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joint_line_req = 1'b0;
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joint_burst_req = 1'b0;
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joint_burst_req = 1'b0;
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joint_flush = 1'b0;
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joint_flush = 1'b0;
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joint_wait = 1'b0;
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joint_wait = 1'b0;
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case (ps)
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case (ps)
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IDLE :
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IDLE :
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begin
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begin
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if (joint_flush_in | joint_buffer_small)
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if (joint_flush_in | joint_buffer_small)
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ns = FLUSH;
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ns = FLUSH;
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else if (joint_ready_out & joint_ready_in & outs_empty)
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else if (joint_ready_out & joint_ready_in & outs_empty)
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ns = READY;
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ns = READY;
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else if (joint_ready_out)
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else if (joint_ready_out)
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begin
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begin
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joint_wait = 1'b1;
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joint_wait = 1'b1;
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ns = READY_OUT;
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ns = READY_OUT;
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end
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end
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else if (fifo_not_ready & joint_ready_in & outs_empty)
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else if (fifo_not_ready & joint_ready_in & outs_empty)
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if (WRITE)
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if (WRITE)
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begin
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begin
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joint_line_req = 1'b1; //from write to read - fill fifo at begining
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joint_line_req = 1'b1; //from write to read - fill fifo at begining
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ns = REQ_LINE;
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ns = REQ_LINE;
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end
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end
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else
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else
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begin
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begin
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joint_burst_req = 1'b1; //from read to write - empty fifo after cross
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joint_burst_req = 1'b1; //from read to write - empty fifo after cross
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ns = REQ_LINE; //1 cycle pulse
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ns = REQ_LINE; //1 cycle pulse
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end
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end
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else
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else
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ns = IDLE;
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ns = IDLE;
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end
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end
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REQ_LINE :
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REQ_LINE :
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begin
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begin
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if (joint_flush_in)
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if (joint_flush_in)
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ns = FLUSH;
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ns = FLUSH;
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else if (joint_line_req_clr)
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else if (joint_line_req_clr)
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begin
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begin
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ns = IDLE;
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ns = IDLE;
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joint_wait = 1'b0;
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joint_wait = 1'b0;
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end
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end
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else
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else
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begin
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begin
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ns = REQ_LINE;
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ns = REQ_LINE;
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joint_wait = 1'b1;
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joint_wait = 1'b1;
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end
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end
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end
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end
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READY_OUT :
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READY_OUT :
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begin
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begin
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joint_wait = 1'b1;
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joint_wait = 1'b1;
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if (joint_cross | page_cross)
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if (joint_cross | page_cross)
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ns = CROSS;
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ns = CROSS;
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else if ((~joint_ready_out) | joint_flush_in | joint_buffer_small)
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else if ((~joint_ready_out) | joint_flush_in | joint_buffer_small)
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ns = FLUSH;
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ns = FLUSH;
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else if (joint_ready_in & outs_empty)
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else if (joint_ready_in & outs_empty)
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begin
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begin
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joint_wait = 1'b0;
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joint_wait = 1'b0;
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ns = RECHK;
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ns = RECHK;
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end
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end
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else
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else
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ns = READY_OUT;
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ns = READY_OUT;
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end
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end
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RECHK :
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RECHK :
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begin
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begin
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if (joint_flush_in | joint_buffer_small)
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if (joint_flush_in | joint_buffer_small)
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ns = FLUSH;
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ns = FLUSH;
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else if (joint_ready_in & joint_ready_out)
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else if (joint_ready_in & joint_ready_out)
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ns = READY;
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ns = READY;
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else if (WRITE)
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else if (WRITE)
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begin
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begin
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joint_line_req = 1'b1; //from write to read - read more data when AHB gets out of align address
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joint_line_req = 1'b1; //from write to read - read more data when AHB gets out of align address
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ns = REQ_LINE;
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ns = REQ_LINE;
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end
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end
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else if (READ)
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else if (READ)
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ns = RECHK;
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ns = RECHK;
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end
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end
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READY :
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READY :
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begin
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begin
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if (joint_cross)
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if (joint_cross)
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begin
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begin
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joint_wait = 1'b1;
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joint_wait = 1'b1;
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ns = READY_OUT;
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ns = READY_OUT;
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end
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end
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else if ((~joint_ready_out) | (~joint_ready_in) | ch_end_flush)
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else if ((~joint_ready_out) | (~joint_ready_in) | ch_end_flush)
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ns = FLUSH;
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ns = FLUSH;
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else
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else
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ns = READY;
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ns = READY;
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end
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end
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CROSS :
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CROSS :
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begin
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begin
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if (joint_buffer_small)
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if (joint_buffer_small)
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ns = FLUSH;
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ns = FLUSH;
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else if (joint_ready_out & (~joint_cross) & outs_empty)
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else if (joint_ready_out & (~joint_cross) & outs_empty)
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begin
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begin
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if (fifo_wr_ready & (fifo_remain <= 'd16)) //rd_gap
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if (fifo_wr_ready & (fifo_remain <= 'd16)) //rd_gap
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begin
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begin
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joint_burst_req = 1'b1; //from read to write - empty fifo after cross
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joint_burst_req = 1'b1; //from read to write - empty fifo after cross
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if (fifo_remain == 'd0)
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if (fifo_remain == 'd0)
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ns = BURST_REQ; //2 cycles pulse
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ns = BURST_REQ; //2 cycles pulse
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else
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else
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ns = REQ_LINE; //1 cycle pulse
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ns = REQ_LINE; //1 cycle pulse
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end
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end
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else
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else
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ns = IDLE;
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ns = IDLE;
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end
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end
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else
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else
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ns = CROSS;
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ns = CROSS;
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end
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end
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BURST_REQ :
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BURST_REQ :
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begin
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begin
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joint_burst_req = 1'b1; //from read to write - empty fifo after cross
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joint_burst_req = 1'b1; //from read to write - empty fifo after cross
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ns = REQ_LINE;
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ns = REQ_LINE;
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end
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end
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FLUSH :
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FLUSH :
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begin
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begin
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joint_flush = 1'b1;
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joint_flush = 1'b1;
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ns = FLUSH;
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ns = FLUSH;
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end
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end
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default :
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default :
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ns = IDLE;
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ns = IDLE;
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endcase
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endcase
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end
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end
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always @(posedge clk or posedge reset)
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always @(posedge clk or posedge reset)
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if (reset)
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if (reset)
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ps <= #1 IDLE;
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ps <= #1 IDLE;
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else if (joint_update)
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else if (joint_update)
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ps <= #1 IDLE;
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ps <= #1 IDLE;
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else
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else
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ps <= #1 ns;
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ps <= #1 ns;
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endmodule
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endmodule
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