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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Author: Eyal Hochberg ////
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//// eyal@provartec.com ////
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//// ////
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//// Downloaded from: http://www.opencores.org ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2010 Provartec LTD ////
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//// www.provartec.com ////
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//// info@provartec.com ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation.////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more////
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//// details. http://www.gnu.org/licenses/lgpl.html ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//---------------------------------------------------------
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//---------------------------------------------------------
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//-- File generated by RobustVerilog parser
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//-- File generated by RobustVerilog parser
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//-- Version: 1.0
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//-- Version: 1.0
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//-- Invoked Fri Mar 25 23:34:54 2011
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//-- Invoked Fri Mar 25 23:34:54 2011
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//--
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//--
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//-- Source file: dma_ch_fifo_ctrl.v
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//-- Source file: dma_ch_fifo_ctrl.v
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//---------------------------------------------------------
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//---------------------------------------------------------
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module dma_axi32_core0_ch_fifo_ctrl (clk,reset,end_swap,joint_in_prog,wr_outstanding,ch_update,fifo_wr,fifo_wdata,fifo_wsize,wr_align,rd_incr,fifo_rd,fifo_rsize,rd_align,wr_incr,wr_single,wr_burst_size,rd_clr_line,wr_clr_line,wr_next_size,fifo_rd_valid,fifo_rdata,fifo_wr_ready,fifo_overflow,fifo_underflow);
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module dma_axi32_core0_ch_fifo_ctrl (clk,reset,end_swap,joint_in_prog,wr_outstanding,ch_update,fifo_wr,fifo_wdata,fifo_wsize,wr_align,rd_incr,fifo_rd,fifo_rsize,rd_align,wr_incr,wr_single,wr_burst_size,rd_clr_line,wr_clr_line,wr_next_size,fifo_rd_valid,fifo_rdata,fifo_wr_ready,fifo_overflow,fifo_underflow);
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input clk;
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input clk;
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input reset;
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input reset;
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input [1:0] end_swap;
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input [1:0] end_swap;
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input joint_in_prog;
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input joint_in_prog;
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input wr_outstanding;
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input wr_outstanding;
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input ch_update;
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input ch_update;
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input fifo_wr;
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input fifo_wr;
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input [32-1:0] fifo_wdata;
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input [32-1:0] fifo_wdata;
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input [3-1:0] fifo_wsize;
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input [3-1:0] fifo_wsize;
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input [2-1:0] wr_align;
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input [2-1:0] wr_align;
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input rd_incr;
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input rd_incr;
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input fifo_rd;
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input fifo_rd;
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input [3-1:0] fifo_rsize;
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input [3-1:0] fifo_rsize;
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input [2-1:0] rd_align;
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input [2-1:0] rd_align;
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input wr_incr;
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input wr_incr;
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input wr_single;
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input wr_single;
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input [7-1:0] wr_burst_size;
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input [7-1:0] wr_burst_size;
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input rd_clr_line;
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input rd_clr_line;
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input wr_clr_line;
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input wr_clr_line;
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input [3-1:0] wr_next_size;
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input [3-1:0] wr_next_size;
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output fifo_rd_valid;
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output fifo_rd_valid;
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output [32-1:0] fifo_rdata;
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output [32-1:0] fifo_rdata;
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output fifo_wr_ready;
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output fifo_wr_ready;
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output fifo_overflow;
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output fifo_overflow;
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output fifo_underflow;
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output fifo_underflow;
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//outputs of wr slicer
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//outputs of wr slicer
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wire slice_wr;
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wire slice_wr;
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wire slice_wr_fifo;
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wire slice_wr_fifo;
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wire [5-1:0] slice_wr_ptr;
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wire [5-1:0] slice_wr_ptr;
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wire [4-1:0] slice_bsel;
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wire [4-1:0] slice_bsel;
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wire [32-1:0] slice_wdata;
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wire [32-1:0] slice_wdata;
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wire [3-1:0] slice_wsize;
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wire [3-1:0] slice_wsize;
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//outputs of rd slicer
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//outputs of rd slicer
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wire slice_rd;
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wire slice_rd;
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wire [32-1:0] slice_rdata;
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wire [32-1:0] slice_rdata;
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wire [3-1:0] slice_rsize;
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wire [3-1:0] slice_rsize;
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wire [5-1:0] slice_rd_ptr;
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wire [5-1:0] slice_rd_ptr;
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wire slice_rd_valid;
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wire slice_rd_valid;
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//outputs of fifo ptr
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//outputs of fifo ptr
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wire [5-1:0] rd_ptr;
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wire [5-1:0] rd_ptr;
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wire [5-1:0] wr_ptr;
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wire [5-1:0] wr_ptr;
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wire [3-1:0] rd_line_remain;
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wire [3-1:0] rd_line_remain;
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wire joint_delay;
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wire joint_delay;
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wire fifo_wr_ready;
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wire fifo_wr_ready;
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wire fifo_overflow;
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wire fifo_overflow;
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wire fifo_underflow;
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wire fifo_underflow;
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//outputs of fifo
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//outputs of fifo
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wire [32-1:0] DOUT;
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wire [32-1:0] DOUT;
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wire fifo_wr_d;
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wire fifo_wr_d;
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reg [32-1:0] fifo_wdata_d;
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reg [32-1:0] fifo_wdata_d;
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wire fifo_wr_valid;
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wire fifo_wr_valid;
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wire [32-1:0] fifo_wdata_valid;
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wire [32-1:0] fifo_wdata_valid;
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assign fifo_wr_valid = fifo_wr;
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assign fifo_wr_valid = fifo_wr;
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assign fifo_wdata_valid = fifo_wdata;
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assign fifo_wdata_valid = fifo_wdata;
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assign fifo_rdata = slice_rdata & {32{slice_rd_valid}};
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assign fifo_rdata = slice_rdata & {32{slice_rd_valid}};
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assign fifo_rd_valid = slice_rd_valid;
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assign fifo_rd_valid = slice_rd_valid;
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dma_axi32_core0_ch_wr_slicer
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dma_axi32_core0_ch_wr_slicer
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dma_axi32_ch_wr_slicer (
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dma_axi32_ch_wr_slicer (
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.clk(clk),
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.clk(clk),
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.reset(reset),
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.reset(reset),
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.ch_update(ch_update),
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.ch_update(ch_update),
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.rd_clr_line(rd_clr_line),
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.rd_clr_line(rd_clr_line),
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.fifo_wr(fifo_wr_valid),
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.fifo_wr(fifo_wr_valid),
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.fifo_wdata(fifo_wdata_valid),
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.fifo_wdata(fifo_wdata_valid),
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.fifo_wsize(fifo_wsize),
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.fifo_wsize(fifo_wsize),
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.wr_align(wr_align),
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.wr_align(wr_align),
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.wr_ptr(wr_ptr),
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.wr_ptr(wr_ptr),
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.rd_incr(rd_incr),
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.rd_incr(rd_incr),
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.end_swap(end_swap),
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.end_swap(end_swap),
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.slice_wr(slice_wr),
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.slice_wr(slice_wr),
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.slice_wr_fifo(slice_wr_fifo),
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.slice_wr_fifo(slice_wr_fifo),
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.slice_wr_ptr(slice_wr_ptr),
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.slice_wr_ptr(slice_wr_ptr),
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.slice_bsel(slice_bsel),
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.slice_bsel(slice_bsel),
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.slice_wdata(slice_wdata),
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.slice_wdata(slice_wdata),
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.slice_wsize(slice_wsize)
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.slice_wsize(slice_wsize)
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);
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);
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dma_axi32_core0_ch_rd_slicer
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dma_axi32_core0_ch_rd_slicer
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dma_axi32_ch_rd_slicer (
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dma_axi32_ch_rd_slicer (
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.clk(clk),
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.clk(clk),
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.reset(reset),
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.reset(reset),
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.fifo_rd(fifo_rd),
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.fifo_rd(fifo_rd),
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.fifo_rdata(DOUT),
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.fifo_rdata(DOUT),
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.fifo_rsize(fifo_rsize),
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.fifo_rsize(fifo_rsize),
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.rd_align(rd_align),
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.rd_align(rd_align),
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.rd_ptr(rd_ptr),
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.rd_ptr(rd_ptr),
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.rd_line_remain(rd_line_remain),
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.rd_line_remain(rd_line_remain),
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.wr_incr(wr_incr),
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.wr_incr(wr_incr),
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.wr_single(wr_single),
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.wr_single(wr_single),
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.slice_rd(slice_rd),
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.slice_rd(slice_rd),
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.slice_rdata(slice_rdata),
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.slice_rdata(slice_rdata),
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.slice_rd_valid(slice_rd_valid),
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.slice_rd_valid(slice_rd_valid),
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.slice_rsize(slice_rsize),
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.slice_rsize(slice_rsize),
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.slice_rd_ptr(slice_rd_ptr)
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.slice_rd_ptr(slice_rd_ptr)
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);
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);
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dma_axi32_core0_ch_fifo_ptr
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dma_axi32_core0_ch_fifo_ptr
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dma_axi32_ch_fifo_ptr (
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dma_axi32_ch_fifo_ptr (
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.clk(clk),
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.clk(clk),
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.reset(reset),
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.reset(reset),
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.joint_in_prog(joint_in_prog),
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.joint_in_prog(joint_in_prog),
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.wr_outstanding(wr_outstanding),
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.wr_outstanding(wr_outstanding),
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.ch_update(ch_update),
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.ch_update(ch_update),
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.fifo_rd(fifo_rd),
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.fifo_rd(fifo_rd),
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.fifo_rsize(fifo_rsize),
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.fifo_rsize(fifo_rsize),
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.slice_wr(slice_wr),
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.slice_wr(slice_wr),
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.slice_wr_fifo(slice_wr_fifo),
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.slice_wr_fifo(slice_wr_fifo),
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.slice_wsize(slice_wsize),
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.slice_wsize(slice_wsize),
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.slice_rd(slice_rd),
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.slice_rd(slice_rd),
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.slice_rsize(slice_rsize),
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.slice_rsize(slice_rsize),
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.rd_clr_line(rd_clr_line),
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.rd_clr_line(rd_clr_line),
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.wr_clr_line(wr_clr_line),
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.wr_clr_line(wr_clr_line),
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.rd_ptr(rd_ptr),
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.rd_ptr(rd_ptr),
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.wr_ptr(wr_ptr),
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.wr_ptr(wr_ptr),
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.rd_line_remain(rd_line_remain),
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.rd_line_remain(rd_line_remain),
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.joint_delay(joint_delay),
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.joint_delay(joint_delay),
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.wr_next_size(wr_next_size),
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.wr_next_size(wr_next_size),
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.wr_burst_size(wr_burst_size),
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.wr_burst_size(wr_burst_size),
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.fifo_wr_ready(fifo_wr_ready),
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.fifo_wr_ready(fifo_wr_ready),
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.fifo_overflow(fifo_overflow),
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.fifo_overflow(fifo_overflow),
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.fifo_underflow(fifo_underflow)
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.fifo_underflow(fifo_underflow)
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);
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);
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dma_axi32_core0_ch_fifo
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dma_axi32_core0_ch_fifo
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dma_axi32_ch_fifo (
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dma_axi32_ch_fifo (
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.CLK(clk),
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.CLK(clk),
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.WR(slice_wr_fifo),
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.WR(slice_wr_fifo),
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.RD(slice_rd),
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.RD(slice_rd),
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.WR_ADDR(slice_wr_ptr[5-1:2] ),
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.WR_ADDR(slice_wr_ptr[5-1:2] ),
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.RD_ADDR(slice_rd_ptr[5-1:2]),
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.RD_ADDR(slice_rd_ptr[5-1:2]),
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.DIN(slice_wdata),
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.DIN(slice_wdata),
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.BSEL(slice_bsel),
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.BSEL(slice_bsel),
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.DOUT(DOUT)
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.DOUT(DOUT)
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);
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);
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endmodule
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endmodule
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