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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Author: Eyal Hochberg ////
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//// eyal@provartec.com ////
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//// ////
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//// Downloaded from: http://www.opencores.org ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2010 Provartec LTD ////
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//// www.provartec.com ////
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//// info@provartec.com ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation.////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more////
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//// details. http://www.gnu.org/licenses/lgpl.html ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//---------------------------------------------------------
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//---------------------------------------------------------
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//-- File generated by RobustVerilog parser
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//-- File generated by RobustVerilog parser
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//-- Version: 1.0
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//-- Version: 1.0
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//-- Invoked Fri Mar 25 23:34:53 2011
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//-- Invoked Fri Mar 25 23:34:53 2011
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//--
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//--
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//-- Source file: dma_ch_offsets.v
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//-- Source file: dma_ch_offsets.v
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//---------------------------------------------------------
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//---------------------------------------------------------
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module dma_axi32_core0_ch_offsets(clk,reset,ch_update,burst_start,burst_last,burst_size,load_req_in_prog,x_size,y_size,x_offset,y_offset,x_remain,clr_remain,ch_end,go_next_line,incr,clr_line,line_empty,empty,start_align,width_align,align);
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module dma_axi32_core0_ch_offsets(clk,reset,ch_update,burst_start,burst_last,burst_size,load_req_in_prog,x_size,y_size,x_offset,y_offset,x_remain,clr_remain,ch_end,go_next_line,incr,clr_line,line_empty,empty,start_align,width_align,align);
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input clk;
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input clk;
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input reset;
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input reset;
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input ch_update;
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input ch_update;
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input burst_start;
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input burst_start;
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input burst_last;
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input burst_last;
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input [7-1:0] burst_size;
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input [7-1:0] burst_size;
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input load_req_in_prog;
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input load_req_in_prog;
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input [10-1:0] x_size;
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input [10-1:0] x_size;
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input [10-`X_BITS-1:0] y_size;
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input [10-`X_BITS-1:0] y_size;
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output [10-1:0] x_offset;
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output [10-1:0] x_offset;
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output [10-`X_BITS-1:0] y_offset;
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output [10-`X_BITS-1:0] y_offset;
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output [10-1:0] x_remain;
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output [10-1:0] x_remain;
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output [10-`X_BITS-1:0] clr_remain;
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output [10-`X_BITS-1:0] clr_remain;
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output ch_end;
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output ch_end;
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output go_next_line;
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output go_next_line;
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input incr;
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input incr;
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input clr_line;
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input clr_line;
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output line_empty;
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output line_empty;
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output empty;
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output empty;
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input [2-1:0] start_align;
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input [2-1:0] start_align;
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input [2-1:0] width_align;
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input [2-1:0] width_align;
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output [2-1:0] align;
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output [2-1:0] align;
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wire update_line;
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wire update_line;
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wire go_next_line;
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wire go_next_line;
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wire line_end_pre;
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wire line_end_pre;
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wire line_empty;
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wire line_empty;
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reg [10-1:0] x_remain;
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reg [10-1:0] x_remain;
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wire ch_end_pre;
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wire ch_end_pre;
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reg ch_end;
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reg ch_end;
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wire ch_update_d;
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wire ch_update_d;
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assign ch_end_pre = burst_start & burst_last;
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assign ch_end_pre = burst_start & burst_last;
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assign go_next_line = 1'b0;
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assign go_next_line = 1'b0;
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assign line_empty = 1'b0;
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assign line_empty = 1'b0;
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assign empty = ch_end_pre | ch_end;
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assign empty = ch_end_pre | ch_end;
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always @(posedge clk or posedge reset)
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always @(posedge clk or posedge reset)
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if (reset)
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if (reset)
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ch_end <= #1 1'b0;
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ch_end <= #1 1'b0;
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else if (ch_update)
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else if (ch_update)
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ch_end <= #1 1'b0;
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ch_end <= #1 1'b0;
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else if (ch_end_pre)
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else if (ch_end_pre)
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ch_end <= #1 1'b1;
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ch_end <= #1 1'b1;
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always @(posedge clk or posedge reset)
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always @(posedge clk or posedge reset)
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if (reset)
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if (reset)
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x_remain <= #1 {10{1'b0}};
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x_remain <= #1 {10{1'b0}};
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else if (ch_update | go_next_line)
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else if (ch_update | go_next_line)
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x_remain <= #1 x_size;
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x_remain <= #1 x_size;
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else if (burst_start & (~load_req_in_prog))
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else if (burst_start & (~load_req_in_prog))
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x_remain <= #1 x_remain - burst_size;
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x_remain <= #1 x_remain - burst_size;
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assign x_offset = {10{1'b0}};
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assign x_offset = {10{1'b0}};
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assign y_offset = {10-`X_BITS{1'b0}};
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assign y_offset = {10-`X_BITS{1'b0}};
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assign clr_remain = {10-`X_BITS{1'b0}};
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assign clr_remain = {10-`X_BITS{1'b0}};
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assign align = start_align;
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assign align = start_align;
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endmodule
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endmodule
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