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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Author: Eyal Hochberg ////
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//// eyal@provartec.com ////
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//// ////
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//// Downloaded from: http://www.opencores.org ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2010 Provartec LTD ////
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//// www.provartec.com ////
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//// info@provartec.com ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation.////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more////
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//// details. http://www.gnu.org/licenses/lgpl.html ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//---------------------------------------------------------
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//---------------------------------------------------------
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//-- File generated by RobustVerilog parser
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//-- File generated by RobustVerilog parser
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//-- Version: 1.0
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//-- Version: 1.0
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//-- Invoked Fri Mar 25 23:34:54 2011
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//-- Invoked Fri Mar 25 23:34:54 2011
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//--
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//--
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//-- Source file: dma_ch_wr_slicer.v
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//-- Source file: dma_ch_wr_slicer.v
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//---------------------------------------------------------
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//---------------------------------------------------------
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module dma_axi32_core0_ch_wr_slicer (clk,reset,ch_update,rd_clr_line,fifo_wr,fifo_wdata,fifo_wsize,wr_align,wr_ptr,rd_incr,end_swap,slice_wr,slice_wr_fifo,slice_wr_ptr,slice_bsel,slice_wdata,slice_wsize);
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module dma_axi32_core0_ch_wr_slicer (clk,reset,ch_update,rd_clr_line,fifo_wr,fifo_wdata,fifo_wsize,wr_align,wr_ptr,rd_incr,end_swap,slice_wr,slice_wr_fifo,slice_wr_ptr,slice_bsel,slice_wdata,slice_wsize);
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input clk;
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input clk;
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input reset;
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input reset;
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input ch_update;
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input ch_update;
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input rd_clr_line;
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input rd_clr_line;
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input fifo_wr;
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input fifo_wr;
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input [32-1:0] fifo_wdata;
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input [32-1:0] fifo_wdata;
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input [3-1:0] fifo_wsize;
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input [3-1:0] fifo_wsize;
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input [2-1:0] wr_align;
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input [2-1:0] wr_align;
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input [5-1:0] wr_ptr;
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input [5-1:0] wr_ptr;
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input rd_incr;
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input rd_incr;
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input [1:0] end_swap;
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input [1:0] end_swap;
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output slice_wr;
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output slice_wr;
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output slice_wr_fifo;
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output slice_wr_fifo;
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output [5-1:0] slice_wr_ptr;
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output [5-1:0] slice_wr_ptr;
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output [4-1:0] slice_bsel;
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output [4-1:0] slice_bsel;
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output [32-1:0] slice_wdata;
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output [32-1:0] slice_wdata;
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output [3-1:0] slice_wsize;
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output [3-1:0] slice_wsize;
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reg [3-1:0] line_remain;
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reg [3-1:0] line_remain;
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wire [3-1:0] join_wsize;
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wire [3-1:0] join_wsize;
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wire [3-1:0] append_wsize;
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wire [3-1:0] append_wsize;
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wire [3-1:0] direct_wsize;
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wire [3-1:0] direct_wsize;
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reg append;
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reg append;
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reg [3-1:0] next_size;
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reg [3-1:0] next_size;
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reg [32-1:0] align_wdata;
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reg [32-1:0] align_wdata;
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reg [32-1:0] align_wdata_d;
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reg [32-1:0] align_wdata_d;
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wire [2-1:0] wr_align_valid;
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wire [2-1:0] wr_align_valid;
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reg [32-1:0] next_wdata;
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reg [32-1:0] next_wdata;
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wire [4-1:0] bsel_dec;
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wire [4-1:0] bsel_dec;
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reg [4-1:0] bsel_shift;
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reg [4-1:0] bsel_shift;
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wire next_wr;
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wire next_wr;
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wire slice_wr_pre;
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wire slice_wr_pre;
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wire [5-1:0] slice_wr_ptr_pre;
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wire [5-1:0] slice_wr_ptr_pre;
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wire [4-1:0] slice_bsel_pre;
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wire [4-1:0] slice_bsel_pre;
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wire [4-1:0] slice_bsel_swap;
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wire [4-1:0] slice_bsel_swap;
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wire [32-1:0] slice_wdata_pre;
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wire [32-1:0] slice_wdata_pre;
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reg [32-1:0] slice_wdata_pre_d;
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reg [32-1:0] slice_wdata_pre_d;
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wire [32-1:0] slice_wdata_swap;
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wire [32-1:0] slice_wdata_swap;
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wire [3-1:0] slice_wsize_pre;
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wire [3-1:0] slice_wsize_pre;
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wire slice_wr;
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wire slice_wr;
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wire slice_wr_fifo;
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wire slice_wr_fifo;
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reg [5-1:0] slice_wr_ptr;
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reg [5-1:0] slice_wr_ptr;
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reg [4-1:0] slice_bsel;
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reg [4-1:0] slice_bsel;
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reg [32-1:0] slice_wdata;
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reg [32-1:0] slice_wdata;
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reg [3-1:0] slice_wsize;
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reg [3-1:0] slice_wsize;
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always @(posedge clk or posedge reset)
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always @(posedge clk or posedge reset)
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if (reset)
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if (reset)
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line_remain <= #1 3'd4;
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line_remain <= #1 3'd4;
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else if (ch_update | rd_clr_line)
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else if (ch_update | rd_clr_line)
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line_remain <= #1 3'd4;
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line_remain <= #1 3'd4;
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else if (slice_wr_pre & (line_remain == slice_wsize_pre))
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else if (slice_wr_pre & (line_remain == slice_wsize_pre))
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line_remain <= #1 3'd4;
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line_remain <= #1 3'd4;
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else if (slice_wr_pre)
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else if (slice_wr_pre)
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line_remain <= #1 line_remain - slice_wsize_pre;
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line_remain <= #1 line_remain - slice_wsize_pre;
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assign join_wsize = next_size + fifo_wsize;
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assign join_wsize = next_size + fifo_wsize;
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prgen_min2 #(3) min2_append(
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prgen_min2 #(3) min2_append(
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.a(join_wsize),
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.a(join_wsize),
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.b(3'd4),
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.b(3'd4),
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.min(append_wsize)
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.min(append_wsize)
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);
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);
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prgen_min2 #(3) min2_direct(
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prgen_min2 #(3) min2_direct(
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.a(line_remain),
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.a(line_remain),
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.b(fifo_wsize),
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.b(fifo_wsize),
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.min(direct_wsize)
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.min(direct_wsize)
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);
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);
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always @(posedge clk or posedge reset)
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always @(posedge clk or posedge reset)
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if (reset)
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if (reset)
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append <= #1 1'b0;
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append <= #1 1'b0;
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else if (next_wr)
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else if (next_wr)
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append <= #1 1'b0;
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append <= #1 1'b0;
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else if (fifo_wr & (slice_wsize_pre == join_wsize))
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else if (fifo_wr & (slice_wsize_pre == join_wsize))
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append <= #1 1'b0;
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append <= #1 1'b0;
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else if (fifo_wr)
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else if (fifo_wr)
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append <= #1 1'b1;
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append <= #1 1'b1;
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always @(posedge clk or posedge reset)
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always @(posedge clk or posedge reset)
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if (reset)
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if (reset)
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next_size <= #1 {3{1'b0}};
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next_size <= #1 {3{1'b0}};
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else if (next_wr)
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else if (next_wr)
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next_size <= #1 {3{1'b0}};
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next_size <= #1 {3{1'b0}};
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else if (fifo_wr & append)
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else if (fifo_wr & append)
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next_size <= #1 join_wsize - append_wsize;
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next_size <= #1 join_wsize - append_wsize;
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else if (fifo_wr)
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else if (fifo_wr)
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next_size <= #1 join_wsize - direct_wsize;
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next_size <= #1 join_wsize - direct_wsize;
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//WDATA
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//WDATA
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always @(posedge clk or posedge reset)
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always @(posedge clk or posedge reset)
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if (reset)
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if (reset)
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align_wdata_d <= #1 {32{1'b0}};
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align_wdata_d <= #1 {32{1'b0}};
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else if (fifo_wr)
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else if (fifo_wr)
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align_wdata_d <= #1 align_wdata;
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align_wdata_d <= #1 align_wdata;
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assign wr_align_valid =
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assign wr_align_valid =
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rd_incr ? wr_align :
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rd_incr ? wr_align :
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wr_align - wr_ptr[2-1:0];
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wr_align - wr_ptr[2-1:0];
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//always @(/*AUTOSENSE*/) - no AUTOSENSE because of fifo_wr
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//always @(/*AUTOSENSE*/) - no AUTOSENSE because of fifo_wr
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always @(fifo_wdata or wr_align_valid or fifo_wr)
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always @(fifo_wdata or wr_align_valid or fifo_wr)
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begin
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begin
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case (wr_align_valid[2-1:0])
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case (wr_align_valid[2-1:0])
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2'd0 : align_wdata = fifo_wdata;
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2'd0 : align_wdata = fifo_wdata;
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2'd1 : align_wdata = {fifo_wdata[7:0], fifo_wdata[31:8]};
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2'd1 : align_wdata = {fifo_wdata[7:0], fifo_wdata[31:8]};
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2'd2 : align_wdata = {fifo_wdata[15:0], fifo_wdata[31:16]};
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2'd2 : align_wdata = {fifo_wdata[15:0], fifo_wdata[31:16]};
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2'd3 : align_wdata = {fifo_wdata[23:0], fifo_wdata[31:24]};
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2'd3 : align_wdata = {fifo_wdata[23:0], fifo_wdata[31:24]};
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endcase
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endcase
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end
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end
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always @(/*AUTOSENSE*/align_wdata or align_wdata_d or next_size)
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always @(/*AUTOSENSE*/align_wdata or align_wdata_d or next_size)
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begin
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begin
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case (next_size[2-1:0])
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case (next_size[2-1:0])
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2'd0 : next_wdata = align_wdata_d;
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2'd0 : next_wdata = align_wdata_d;
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2'd1 : next_wdata = {align_wdata[31:8], align_wdata_d[7:0]};
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2'd1 : next_wdata = {align_wdata[31:8], align_wdata_d[7:0]};
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2'd2 : next_wdata = {align_wdata[31:16], align_wdata_d[15:0]};
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2'd2 : next_wdata = {align_wdata[31:16], align_wdata_d[15:0]};
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2'd3 : next_wdata = {align_wdata[31:24], align_wdata_d[23:0]};
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2'd3 : next_wdata = {align_wdata[31:24], align_wdata_d[23:0]};
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endcase
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endcase
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end
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end
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//BSEL
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//BSEL
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assign bsel_dec =
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assign bsel_dec =
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slice_wsize == 4'd1 ? 4'b0001 :
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slice_wsize == 4'd1 ? 4'b0001 :
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slice_wsize == 4'd2 ? 4'b0011 :
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slice_wsize == 4'd2 ? 4'b0011 :
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slice_wsize == 4'd3 ? 4'b0111 :
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slice_wsize == 4'd3 ? 4'b0111 :
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slice_wsize == 4'd4 ? 4'b1111 :
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slice_wsize == 4'd4 ? 4'b1111 :
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{4{1'b0}};
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{4{1'b0}};
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always @(/*AUTOSENSE*/bsel_dec or wr_ptr)
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always @(/*AUTOSENSE*/bsel_dec or wr_ptr)
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begin
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begin
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case (wr_ptr[2-1:0])
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case (wr_ptr[2-1:0])
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2'd0 : bsel_shift = bsel_dec;
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2'd0 : bsel_shift = bsel_dec;
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2'd1 : bsel_shift = {bsel_dec[2:0], 1'b0};
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2'd1 : bsel_shift = {bsel_dec[2:0], 1'b0};
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2'd2 : bsel_shift = {bsel_dec[1:0], 2'b0};
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2'd2 : bsel_shift = {bsel_dec[1:0], 2'b0};
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2'd3 : bsel_shift = {bsel_dec[0], 3'b0};
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2'd3 : bsel_shift = {bsel_dec[0], 3'b0};
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endcase
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endcase
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end
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end
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//CMD
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//CMD
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assign next_wr = (~fifo_wr) & (|next_size);
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assign next_wr = (~fifo_wr) & (|next_size);
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assign slice_wr_pre = fifo_wr | next_wr;
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assign slice_wr_pre = fifo_wr | next_wr;
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assign slice_wsize_pre =
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assign slice_wsize_pre =
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next_wr ? next_size :
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next_wr ? next_size :
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append ? append_wsize : direct_wsize;
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append ? append_wsize : direct_wsize;
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assign slice_wr_ptr_pre = wr_ptr;
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assign slice_wr_ptr_pre = wr_ptr;
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assign slice_wdata_pre = append ? next_wdata : align_wdata;
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assign slice_wdata_pre = append ? next_wdata : align_wdata;
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assign slice_bsel_pre = bsel_shift;
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assign slice_bsel_pre = bsel_shift;
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prgen_delay #(1) delay_wr0(.clk(clk), .reset(reset), .din(slice_wr_pre), .dout(slice_wr));
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prgen_delay #(1) delay_wr0(.clk(clk), .reset(reset), .din(slice_wr_pre), .dout(slice_wr));
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prgen_delay #(1) delay_wr(.clk(clk), .reset(reset), .din(slice_wr), .dout(slice_wr_fifo));
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prgen_delay #(1) delay_wr(.clk(clk), .reset(reset), .din(slice_wr), .dout(slice_wr_fifo));
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always @(posedge clk or posedge reset)
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always @(posedge clk or posedge reset)
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if (reset)
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if (reset)
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begin
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begin
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slice_wsize <= #1 {3{1'b0}};
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slice_wsize <= #1 {3{1'b0}};
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slice_wdata_pre_d <= #1 {32{1'b0}};
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slice_wdata_pre_d <= #1 {32{1'b0}};
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end
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end
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else if (slice_wr_pre)
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else if (slice_wr_pre)
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begin
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begin
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slice_wsize <= #1 slice_wsize_pre;
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slice_wsize <= #1 slice_wsize_pre;
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slice_wdata_pre_d <= #1 slice_wdata_pre;
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slice_wdata_pre_d <= #1 slice_wdata_pre;
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end
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end
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prgen_swap32 swap32(
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prgen_swap32 swap32(
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.end_swap(end_swap),
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.end_swap(end_swap),
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.data_in(slice_wdata_pre_d),
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.data_in(slice_wdata_pre_d),
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.data_out(slice_wdata_swap),
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.data_out(slice_wdata_swap),
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.bsel_in(slice_bsel_pre),
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.bsel_in(slice_bsel_pre),
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.bsel_out(slice_bsel_swap)
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.bsel_out(slice_bsel_swap)
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);
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);
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always @(posedge clk or posedge reset)
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always @(posedge clk or posedge reset)
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if (reset)
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if (reset)
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begin
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begin
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slice_wdata <= #1 {32{1'b0}};
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slice_wdata <= #1 {32{1'b0}};
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slice_wr_ptr <= #1 {5{1'b0}};
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slice_wr_ptr <= #1 {5{1'b0}};
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slice_bsel <= #1 {4{1'b0}};
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slice_bsel <= #1 {4{1'b0}};
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end
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end
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else if (slice_wr)
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else if (slice_wr)
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begin
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begin
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slice_wdata <= #1 slice_wdata_swap;
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slice_wdata <= #1 slice_wdata_swap;
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slice_wr_ptr <= #1 slice_wr_ptr_pre;
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slice_wr_ptr <= #1 slice_wr_ptr_pre;
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slice_bsel <= #1 slice_bsel_swap;
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slice_bsel <= #1 slice_bsel_swap;
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end
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end
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endmodule
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endmodule
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