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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Author: Eyal Hochberg ////
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//// eyal@provartec.com ////
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//// ////
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//// Downloaded from: http://www.opencores.org ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2010 Provartec LTD ////
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//// www.provartec.com ////
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//// info@provartec.com ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation.////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more////
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//// details. http://www.gnu.org/licenses/lgpl.html ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//---------------------------------------------------------
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//---------------------------------------------------------
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//-- File generated by RobustVerilog parser
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//-- File generated by RobustVerilog parser
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//-- Version: 1.0
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//-- Version: 1.0
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//-- Invoked Fri Mar 25 23:34:51 2011
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//-- Invoked Fri Mar 25 23:34:51 2011
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//--
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//--
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//-- Source file: dma_core_ctrl.v
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//-- Source file: dma_core_ctrl.v
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//---------------------------------------------------------
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//---------------------------------------------------------
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module dma_axi32_core0_ctrl(clk,reset,ch_go,cmd_full,cmd_pending,joint_req,ch_num,ch_num_resp,go_next_line,periph_clr_valid,periph_clr,periph_clr_last,periph_delay,clr_stall,tokens,ch_ready,ch_last,burst_start,finish,busy,hold);
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module dma_axi32_core0_ctrl(clk,reset,ch_go,cmd_full,cmd_pending,joint_req,ch_num,ch_num_resp,go_next_line,periph_clr_valid,periph_clr,periph_clr_last,periph_delay,clr_stall,tokens,ch_ready,ch_last,burst_start,finish,busy,hold);
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input clk;
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input clk;
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input reset;
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input reset;
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input ch_go;
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input ch_go;
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input cmd_full;
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input cmd_full;
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input cmd_pending;
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input cmd_pending;
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input joint_req;
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input joint_req;
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input [2:0] ch_num;
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input [2:0] ch_num;
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input [2:0] ch_num_resp;
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input [2:0] ch_num_resp;
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input go_next_line;
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input go_next_line;
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input periph_clr_valid;
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input periph_clr_valid;
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input periph_clr;
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input periph_clr;
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input periph_clr_last;
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input periph_clr_last;
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input [`DELAY_BITS-1:0] periph_delay;
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input [`DELAY_BITS-1:0] periph_delay;
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input clr_stall;
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input clr_stall;
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input [`TOKEN_BITS-1:0] tokens;
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input [`TOKEN_BITS-1:0] tokens;
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input ch_ready;
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input ch_ready;
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input ch_last;
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input ch_last;
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output burst_start;
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output burst_start;
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output finish;
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output finish;
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output busy;
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output busy;
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input hold;
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input hold;
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reg burst_start;
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reg burst_start;
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reg finish;
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reg finish;
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wire tokens_remain;
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wire tokens_remain;
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reg tokens_remain_reg;
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reg tokens_remain_reg;
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reg [`TOKEN_BITS-1:0] tokens_counter;
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reg [`TOKEN_BITS-1:0] tokens_counter;
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wire stall;
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wire stall;
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reg joint_ctrl_reg;
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reg joint_ctrl_reg;
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wire joint_ctrl;
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wire joint_ctrl;
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reg [`DELAY_BITS-1:0] delay_counter;
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reg [`DELAY_BITS-1:0] delay_counter;
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wire periph_clr_ch;
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wire periph_clr_ch;
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wire periph_clr_last_ch;
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wire periph_clr_last_ch;
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wire go_next_line_d;
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wire go_next_line_d;
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reg [2:0] ps;
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reg [2:0] ps;
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reg [2:0] ns;
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reg [2:0] ns;
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parameter IDLE = 3'd0;
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parameter IDLE = 3'd0;
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parameter CMD = 3'd1;
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parameter CMD = 3'd1;
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parameter WAIT_CLR = 3'd2;
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parameter WAIT_CLR = 3'd2;
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parameter WAIT_DELAY = 3'd3;
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parameter WAIT_DELAY = 3'd3;
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parameter STALL = 3'd4;
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parameter STALL = 3'd4;
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assign busy = ps != IDLE;
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assign busy = ps != IDLE;
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assign periph_clr_ch = periph_clr_valid & periph_clr & (ch_num == ch_num_resp);
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assign periph_clr_ch = periph_clr_valid & periph_clr & (ch_num == ch_num_resp);
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assign periph_clr_last_ch = periph_clr_valid & periph_clr_last & (ch_num == ch_num_resp);
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assign periph_clr_last_ch = periph_clr_valid & periph_clr_last & (ch_num == ch_num_resp);
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assign go_next_line_d = 1'b0;
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assign go_next_line_d = 1'b0;
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always @(posedge clk or posedge reset)
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always @(posedge clk or posedge reset)
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if (reset)
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if (reset)
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joint_ctrl_reg <= #1 1'b0;
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joint_ctrl_reg <= #1 1'b0;
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else if (finish)
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else if (finish)
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joint_ctrl_reg <= #1 1'b0;
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joint_ctrl_reg <= #1 1'b0;
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else if (ch_go)
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else if (ch_go)
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joint_ctrl_reg <= #1 joint_req;
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joint_ctrl_reg <= #1 joint_req;
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assign joint_ctrl = joint_ctrl_reg;
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assign joint_ctrl = joint_ctrl_reg;
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assign tokens_remain = (|tokens_counter) | ch_last;
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assign tokens_remain = (|tokens_counter) | ch_last;
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always @(posedge clk or posedge reset)
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always @(posedge clk or posedge reset)
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if (reset)
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if (reset)
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tokens_counter <= #1 {`TOKEN_BITS{1'b0}};
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tokens_counter <= #1 {`TOKEN_BITS{1'b0}};
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else if (ch_go)
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else if (ch_go)
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tokens_counter <= #1 tokens;
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tokens_counter <= #1 tokens;
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else if (burst_start & (|tokens_counter))
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else if (burst_start & (|tokens_counter))
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tokens_counter <= #1 tokens_counter - 1'b1;
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tokens_counter <= #1 tokens_counter - 1'b1;
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always @(posedge clk or posedge reset)
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always @(posedge clk or posedge reset)
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if (reset)
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if (reset)
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delay_counter <= #1 {`DELAY_BITS{1'b0}};
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delay_counter <= #1 {`DELAY_BITS{1'b0}};
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else if (periph_clr_ch)
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else if (periph_clr_ch)
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delay_counter <= #1 periph_delay;
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delay_counter <= #1 periph_delay;
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else if (|delay_counter)
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else if (|delay_counter)
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delay_counter <= #1 delay_counter - 1'b1;
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delay_counter <= #1 delay_counter - 1'b1;
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assign stall = cmd_pending | cmd_full | go_next_line_d;
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assign stall = cmd_pending | cmd_full | go_next_line_d;
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always @(/*AUTOSENSE*/ch_go or ch_last or ch_ready or clr_stall
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always @(/*AUTOSENSE*/ch_go or ch_last or ch_ready or clr_stall
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or delay_counter or go_next_line_d or hold or joint_ctrl
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or delay_counter or go_next_line_d or hold or joint_ctrl
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or joint_req or periph_clr_ch or periph_clr_last_ch
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or joint_req or periph_clr_ch or periph_clr_last_ch
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or periph_clr_valid or periph_delay or ps or stall
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or periph_clr_valid or periph_delay or ps or stall
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or tokens_remain)
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or tokens_remain)
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begin
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begin
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ns = IDLE;
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ns = IDLE;
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burst_start = 1'b0;
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burst_start = 1'b0;
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finish = 1'b0;
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finish = 1'b0;
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case (ps)
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case (ps)
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IDLE :
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IDLE :
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begin
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begin
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if (ch_go)
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if (ch_go)
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begin
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begin
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if (!ch_ready)
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if (!ch_ready)
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begin
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begin
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ns = IDLE;
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ns = IDLE;
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finish = 1'b1;
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finish = 1'b1;
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end
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end
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else if (stall)
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else if (stall)
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ns = STALL;
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ns = STALL;
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else
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else
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ns = CMD;
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ns = CMD;
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end
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end
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else
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else
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ns = IDLE;
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ns = IDLE;
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end
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end
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CMD :
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CMD :
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begin
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begin
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if (joint_req ^ joint_ctrl) //change in joint_req
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if (joint_req ^ joint_ctrl) //change in joint_req
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begin
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begin
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ns = IDLE;
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ns = IDLE;
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finish = 1'b1;
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finish = 1'b1;
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end
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end
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else if ((clr_stall | hold) & tokens_remain)
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else if ((clr_stall | hold) & tokens_remain)
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ns = CMD;
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ns = CMD;
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else if (ch_ready & tokens_remain)
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else if (ch_ready & tokens_remain)
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begin
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begin
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if (stall)
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if (stall)
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ns = STALL;
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ns = STALL;
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else
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else
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begin
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begin
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burst_start = 1'b1;
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burst_start = 1'b1;
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ns = WAIT_CLR;
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ns = WAIT_CLR;
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end
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end
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end
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end
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else if (ch_last & (~ch_ready))
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else if (ch_last & (~ch_ready))
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ns = CMD;
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ns = CMD;
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else
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else
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begin
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begin
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ns = IDLE;
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ns = IDLE;
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finish = 1'b1;
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finish = 1'b1;
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end
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end
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end
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end
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WAIT_CLR :
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WAIT_CLR :
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begin
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begin
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if ((|periph_delay) & periph_clr_valid) //don't wait for clr if not valid (block clr)
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if ((|periph_delay) & periph_clr_valid) //don't wait for clr if not valid (block clr)
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begin
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begin
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if (periph_clr_last_ch) //release if load cmd
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if (periph_clr_last_ch) //release if load cmd
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begin
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begin
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ns = IDLE;
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ns = IDLE;
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finish = 1'b1;
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finish = 1'b1;
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end
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end
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else if (periph_clr_ch)
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else if (periph_clr_ch)
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ns = WAIT_DELAY;
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ns = WAIT_DELAY;
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else
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else
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ns = WAIT_CLR;
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ns = WAIT_CLR;
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end
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end
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//memory - allow command depth
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//memory - allow command depth
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else if (!tokens_remain)
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else if (!tokens_remain)
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begin
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begin
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ns = IDLE;
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ns = IDLE;
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finish = 1'b1;
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finish = 1'b1;
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end
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end
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else
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else
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ns = WAIT_DELAY;
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ns = WAIT_DELAY;
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end
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end
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WAIT_DELAY :
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WAIT_DELAY :
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begin
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begin
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if (go_next_line_d) //delay in case of cmd split (cross page)
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if (go_next_line_d) //delay in case of cmd split (cross page)
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ns = WAIT_DELAY;
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ns = WAIT_DELAY;
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else if (delay_counter == 'd0)
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else if (delay_counter == 'd0)
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ns = STALL;
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ns = STALL;
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else
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else
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ns = WAIT_DELAY;
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ns = WAIT_DELAY;
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end
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end
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STALL :
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STALL :
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begin
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begin
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if (ch_ready & tokens_remain)
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if (ch_ready & tokens_remain)
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begin
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begin
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if (stall)
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if (stall)
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ns = STALL;
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ns = STALL;
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else
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else
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ns = CMD;
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ns = CMD;
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end
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end
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else if (ch_last & (~ch_ready))
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else if (ch_last & (~ch_ready))
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ns = CMD;
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ns = CMD;
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else
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else
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begin
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begin
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ns = IDLE;
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ns = IDLE;
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finish = 1'b1;
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finish = 1'b1;
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end
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end
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end
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end
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default :
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default :
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begin
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begin
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ns = IDLE;
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ns = IDLE;
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end
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end
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endcase
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endcase
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end
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end
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always @(posedge clk or posedge reset)
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always @(posedge clk or posedge reset)
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if (reset)
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if (reset)
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ps <= #1 IDLE;
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ps <= #1 IDLE;
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else
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else
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ps <= #1 ns;
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ps <= #1 ns;
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endmodule
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endmodule
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