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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Author: Eyal Hochberg ////
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//// eyal@provartec.com ////
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//// ////
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//// Downloaded from: http://www.opencores.org ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2010 Provartec LTD ////
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//// www.provartec.com ////
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//// info@provartec.com ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation.////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more////
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//// details. http://www.gnu.org/licenses/lgpl.html ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//---------------------------------------------------------
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//---------------------------------------------------------
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//-- File generated by RobustVerilog parser
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//-- File generated by RobustVerilog parser
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//-- Version: 1.0
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//-- Version: 1.0
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//-- Invoked Fri Mar 25 23:34:51 2011
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//-- Invoked Fri Mar 25 23:34:51 2011
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//--
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//--
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//-- Source file: prgen_joint_stall.v
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//-- Source file: prgen_joint_stall.v
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//---------------------------------------------------------
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//---------------------------------------------------------
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module prgen_joint_stall(clk,reset,joint_req_out,rd_transfer,rd_transfer_size,ch_fifo_rd,data_fullness_pre,HOLD,joint_fifo_rd_valid,rd_transfer_size_joint,rd_transfer_full,joint_stall);
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module prgen_joint_stall(clk,reset,joint_req_out,rd_transfer,rd_transfer_size,ch_fifo_rd,data_fullness_pre,HOLD,joint_fifo_rd_valid,rd_transfer_size_joint,rd_transfer_full,joint_stall);
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parameter SIZE_BITS = 1;
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parameter SIZE_BITS = 1;
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input clk;
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input clk;
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input reset;
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input reset;
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input joint_req_out;
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input joint_req_out;
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input rd_transfer;
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input rd_transfer;
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input [SIZE_BITS-1:0] rd_transfer_size;
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input [SIZE_BITS-1:0] rd_transfer_size;
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input ch_fifo_rd;
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input ch_fifo_rd;
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input [2:0] data_fullness_pre;
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input [2:0] data_fullness_pre;
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input HOLD;
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input HOLD;
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output joint_fifo_rd_valid;
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output joint_fifo_rd_valid;
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output [SIZE_BITS-1:0] rd_transfer_size_joint;
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output [SIZE_BITS-1:0] rd_transfer_size_joint;
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output rd_transfer_full;
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output rd_transfer_full;
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output joint_stall;
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output joint_stall;
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wire rd_transfer_joint;
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wire rd_transfer_joint;
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wire joint_fifo_rd;
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wire joint_fifo_rd;
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wire joint_fifo_rd_valid;
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wire joint_fifo_rd_valid;
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wire [2:0] count_ch_fifo_pre;
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wire [2:0] count_ch_fifo_pre;
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reg [2:0] count_ch_fifo;
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reg [2:0] count_ch_fifo;
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wire joint_stall_pre;
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wire joint_stall_pre;
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reg joint_stall_reg;
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reg joint_stall_reg;
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wire joint_not_ready_pre;
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wire joint_not_ready_pre;
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wire joint_not_ready;
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wire joint_not_ready;
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wire [SIZE_BITS-1:0] rd_transfer_size_joint;
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wire [SIZE_BITS-1:0] rd_transfer_size_joint;
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wire rd_transfer_full;
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wire rd_transfer_full;
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reg [2:0] joint_rd_stall_num;
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reg [2:0] joint_rd_stall_num;
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wire joint_rd_stall;
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wire joint_rd_stall;
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assign rd_transfer_joint = joint_req_out & rd_transfer;
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assign rd_transfer_joint = joint_req_out & rd_transfer;
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prgen_delay #(2) delay_joint_fifo_rd (.clk(clk), .reset(reset), .din(rd_transfer_joint), .dout(joint_fifo_rd));
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prgen_delay #(2) delay_joint_fifo_rd (.clk(clk), .reset(reset), .din(rd_transfer_joint), .dout(joint_fifo_rd));
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assign count_ch_fifo_pre = count_ch_fifo + rd_transfer_joint - ch_fifo_rd;
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assign count_ch_fifo_pre = count_ch_fifo + rd_transfer_joint - ch_fifo_rd;
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//count fullness of channel's fifo
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//count fullness of channel's fifo
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always @(posedge clk or posedge reset)
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always @(posedge clk or posedge reset)
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if (reset)
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if (reset)
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count_ch_fifo <= #1 3'd0;
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count_ch_fifo <= #1 3'd0;
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else if (joint_req_out & (rd_transfer_joint | ch_fifo_rd))
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else if (joint_req_out & (rd_transfer_joint | ch_fifo_rd))
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count_ch_fifo <= #1 count_ch_fifo_pre;
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count_ch_fifo <= #1 count_ch_fifo_pre;
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//prevent read channel to overflow the channel's fifo
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//prevent read channel to overflow the channel's fifo
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assign joint_stall_pre = joint_req_out & ((count_ch_fifo_pre > 'd2) | ((count_ch_fifo_pre == 'd2) & (data_fullness_pre > 'd1)) | HOLD);
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assign joint_stall_pre = joint_req_out & ((count_ch_fifo_pre > 'd2) | ((count_ch_fifo_pre == 'd2) & (data_fullness_pre > 'd1)) | HOLD);
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//prevent write channel to overflow the wr data fifo
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//prevent write channel to overflow the wr data fifo
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assign joint_not_ready_pre = joint_req_out & (data_fullness_pre > 'd1) & (~(rd_transfer_joint & joint_stall_pre));
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assign joint_not_ready_pre = joint_req_out & (data_fullness_pre > 'd1) & (~(rd_transfer_joint & joint_stall_pre));
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always @(posedge clk or posedge reset)
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always @(posedge clk or posedge reset)
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if (reset)
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if (reset)
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joint_stall_reg <= #1 1'b0;
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joint_stall_reg <= #1 1'b0;
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else if (joint_stall_pre)
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else if (joint_stall_pre)
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joint_stall_reg <= #1 1'b1;
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joint_stall_reg <= #1 1'b1;
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else if (count_ch_fifo_pre == 'd0)
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else if (count_ch_fifo_pre == 'd0)
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joint_stall_reg <= #1 1'b0;
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joint_stall_reg <= #1 1'b0;
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assign joint_stall = joint_stall_reg | (joint_req_out & HOLD);
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assign joint_stall = joint_stall_reg | (joint_req_out & HOLD);
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prgen_delay #(1) delay_joint_not_ready (.clk(clk), .reset(reset), .din(joint_not_ready_pre), .dout(joint_not_ready));
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prgen_delay #(1) delay_joint_not_ready (.clk(clk), .reset(reset), .din(joint_not_ready_pre), .dout(joint_not_ready));
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prgen_fifo #(SIZE_BITS, 2)
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prgen_fifo #(SIZE_BITS, 2)
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rd_transfer_fifo(
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rd_transfer_fifo(
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.clk(clk),
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.clk(clk),
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.reset(reset),
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.reset(reset),
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.push(rd_transfer_joint),
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.push(rd_transfer_joint),
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.pop(joint_fifo_rd_valid),
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.pop(joint_fifo_rd_valid),
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.din(rd_transfer_size),
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.din(rd_transfer_size),
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.dout(rd_transfer_size_joint),
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.dout(rd_transfer_size_joint),
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.empty(),
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.empty(),
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.full(rd_transfer_full)
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.full(rd_transfer_full)
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);
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);
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prgen_stall #(3) stall_joint_fifo_rd (.clk(clk), .reset(reset), .din(joint_fifo_rd), .stall(joint_not_ready), .dout(joint_fifo_rd_valid));
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prgen_stall #(3) stall_joint_fifo_rd (.clk(clk), .reset(reset), .din(joint_fifo_rd), .stall(joint_not_ready), .dout(joint_fifo_rd_valid));
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endmodule
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endmodule
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