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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Author: Eyal Hochberg ////
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//// eyal@provartec.com ////
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//// ////
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//// Downloaded from: http://www.opencores.org ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2010 Provartec LTD ////
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//// www.provartec.com ////
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//// info@provartec.com ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation.////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more////
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//// details. http://www.gnu.org/licenses/lgpl.html ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//---------------------------------------------------------
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//---------------------------------------------------------
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//-- File generated by RobustVerilog parser
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//-- File generated by RobustVerilog parser
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//-- Version: 1.0
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//-- Version: 1.0
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//-- Invoked Fri Mar 25 23:34:53 2011
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//-- Invoked Fri Mar 25 23:34:53 2011
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//--
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//--
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//-- Source file: prgen_rawstat.v
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//-- Source file: prgen_rawstat.v
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//---------------------------------------------------------
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//---------------------------------------------------------
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module prgen_rawstat (clk,reset,clear,write,pwdata,int_bus,rawstat);
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module prgen_rawstat (clk,reset,clear,write,pwdata,int_bus,rawstat);
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parameter SIZE = 32;
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parameter SIZE = 32;
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input clk;
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input clk;
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input reset;
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input reset;
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input clear;
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input clear;
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input write;
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input write;
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input [SIZE-1:0] pwdata;
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input [SIZE-1:0] pwdata;
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input [SIZE-1:0] int_bus;
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input [SIZE-1:0] int_bus;
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output [SIZE-1:0] rawstat;
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output [SIZE-1:0] rawstat;
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reg [SIZE-1:0] rawstat;
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reg [SIZE-1:0] rawstat;
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wire [SIZE-1:0] write_bus;
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wire [SIZE-1:0] write_bus;
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wire [SIZE-1:0] clear_bus;
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wire [SIZE-1:0] clear_bus;
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assign write_bus = {SIZE{write}} & pwdata;
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assign write_bus = {SIZE{write}} & pwdata;
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assign clear_bus = {SIZE{clear}} & pwdata;
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assign clear_bus = {SIZE{clear}} & pwdata;
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always @(posedge clk or posedge reset)
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always @(posedge clk or posedge reset)
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if (reset)
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if (reset)
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rawstat <= #1 {SIZE{1'b0}};
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rawstat <= #1 {SIZE{1'b0}};
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else
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else
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rawstat <= #1 (rawstat | int_bus | write_bus) & (~clear_bus);
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rawstat <= #1 (rawstat | int_bus | write_bus) & (~clear_bus);
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endmodule
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endmodule
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