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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Author: Eyal Hochberg ////
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//// eyal@provartec.com ////
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//// ////
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//// Downloaded from: http://www.opencores.org ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2010 Provartec LTD ////
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//// www.provartec.com ////
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//// info@provartec.com ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation.////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more////
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//// details. http://www.gnu.org/licenses/lgpl.html ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//---------------------------------------------------------
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//---------------------------------------------------------
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//-- File generated by RobustVerilog parser
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//-- File generated by RobustVerilog parser
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//-- Version: 1.0
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//-- Version: 1.0
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//-- Invoked Fri Mar 25 23:36:52 2011
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//-- Invoked Fri Mar 25 23:36:52 2011
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//--
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//--
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//-- Source file: dma.v
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//-- Source file: dma.v
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//---------------------------------------------------------
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//---------------------------------------------------------
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module dma_axi64(clk,reset,scan_en,idle,INT,periph_tx_req,periph_tx_clr,periph_rx_req,periph_rx_clr,pclken,psel,penable,paddr,pwrite,pwdata,prdata,pslverr,pready,AWID0,AWADDR0,AWLEN0,AWSIZE0,AWVALID0,AWREADY0,WID0,WDATA0,WSTRB0,WLAST0,WVALID0,WREADY0,BID0,BRESP0,BVALID0,BREADY0,ARID0,ARADDR0,ARLEN0,ARSIZE0,ARVALID0,ARREADY0,RID0,RDATA0,RRESP0,RLAST0,RVALID0,RREADY0);
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module dma_axi64(clk,reset,scan_en,idle,INT,periph_tx_req,periph_tx_clr,periph_rx_req,periph_rx_clr,pclken,psel,penable,paddr,pwrite,pwdata,prdata,pslverr,pready,AWID0,AWADDR0,AWLEN0,AWSIZE0,AWVALID0,AWREADY0,WID0,WDATA0,WSTRB0,WLAST0,WVALID0,WREADY0,BID0,BRESP0,BVALID0,BREADY0,ARID0,ARADDR0,ARLEN0,ARSIZE0,ARVALID0,ARREADY0,RID0,RDATA0,RRESP0,RLAST0,RVALID0,RREADY0);
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`include "dma_axi64_defines.v"
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`include "dma_axi64_defines.v"
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input clk;
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input clk;
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input reset;
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input reset;
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input scan_en;
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input scan_en;
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output idle;
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output idle;
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output [1-1:0] INT;
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output [1-1:0] INT;
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input [31:1] periph_tx_req;
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input [31:1] periph_tx_req;
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output [31:1] periph_tx_clr;
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output [31:1] periph_tx_clr;
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input [31:1] periph_rx_req;
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input [31:1] periph_rx_req;
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output [31:1] periph_rx_clr;
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output [31:1] periph_rx_clr;
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input pclken;
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input pclken;
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input psel;
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input psel;
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input penable;
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input penable;
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input [12:0] paddr;
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input [12:0] paddr;
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input pwrite;
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input pwrite;
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input [31:0] pwdata;
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input [31:0] pwdata;
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output [31:0] prdata;
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output [31:0] prdata;
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output pslverr;
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output pslverr;
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output pready;
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output pready;
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output [`ID_BITS-1:0] AWID0;
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output [`ID_BITS-1:0] AWID0;
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output [32-1:0] AWADDR0;
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output [32-1:0] AWADDR0;
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output [`LEN_BITS-1:0] AWLEN0;
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output [`LEN_BITS-1:0] AWLEN0;
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output [`SIZE_BITS-1:0] AWSIZE0;
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output [`SIZE_BITS-1:0] AWSIZE0;
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output AWVALID0;
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output AWVALID0;
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input AWREADY0;
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input AWREADY0;
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output [`ID_BITS-1:0] WID0;
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output [`ID_BITS-1:0] WID0;
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output [64-1:0] WDATA0;
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output [64-1:0] WDATA0;
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output [64/8-1:0] WSTRB0;
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output [64/8-1:0] WSTRB0;
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output WLAST0;
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output WLAST0;
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output WVALID0;
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output WVALID0;
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input WREADY0;
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input WREADY0;
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input [`ID_BITS-1:0] BID0;
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input [`ID_BITS-1:0] BID0;
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input [1:0] BRESP0;
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input [1:0] BRESP0;
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input BVALID0;
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input BVALID0;
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output BREADY0;
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output BREADY0;
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output [`ID_BITS-1:0] ARID0;
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output [`ID_BITS-1:0] ARID0;
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output [32-1:0] ARADDR0;
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output [32-1:0] ARADDR0;
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output [`LEN_BITS-1:0] ARLEN0;
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output [`LEN_BITS-1:0] ARLEN0;
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output [`SIZE_BITS-1:0] ARSIZE0;
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output [`SIZE_BITS-1:0] ARSIZE0;
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output ARVALID0;
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output ARVALID0;
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input ARREADY0;
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input ARREADY0;
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input [`ID_BITS-1:0] RID0;
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input [`ID_BITS-1:0] RID0;
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input [64-1:0] RDATA0;
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input [64-1:0] RDATA0;
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input [1:0] RRESP0;
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input [1:0] RRESP0;
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input RLAST0;
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input RLAST0;
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input RVALID0;
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input RVALID0;
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output RREADY0;
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output RREADY0;
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wire rd_port_num0;
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wire rd_port_num0;
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wire wr_port_num0;
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wire wr_port_num0;
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wire rd_port_num1;
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wire rd_port_num1;
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wire wr_port_num1;
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wire wr_port_num1;
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wire slv_rd_port_num0;
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wire slv_rd_port_num0;
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wire slv_wr_port_num0;
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wire slv_wr_port_num0;
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wire slv_rd_port_num1;
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wire slv_rd_port_num1;
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wire slv_wr_port_num1;
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wire slv_wr_port_num1;
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assign M0_AWID = 1'b0;
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assign M0_AWID = 1'b0;
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assign M0_WID = 1'b0;
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assign M0_WID = 1'b0;
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assign M0_ARID = 1'b0;
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assign M0_ARID = 1'b0;
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wire [`ID_BITS-1:0] M0_AWID;
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wire [`ID_BITS-1:0] M0_AWID;
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wire [32-1:0] M0_AWADDR;
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wire [32-1:0] M0_AWADDR;
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wire [`LEN_BITS-1:0] M0_AWLEN;
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wire [`LEN_BITS-1:0] M0_AWLEN;
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wire [`SIZE_BITS-1:0] M0_AWSIZE;
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wire [`SIZE_BITS-1:0] M0_AWSIZE;
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wire M0_AWVALID;
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wire M0_AWVALID;
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wire M0_AWREADY;
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wire M0_AWREADY;
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wire [`ID_BITS-1:0] M0_WID;
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wire [`ID_BITS-1:0] M0_WID;
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wire [64-1:0] M0_WDATA;
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wire [64-1:0] M0_WDATA;
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wire [64/8-1:0] M0_WSTRB;
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wire [64/8-1:0] M0_WSTRB;
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wire M0_WLAST;
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wire M0_WLAST;
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wire M0_WVALID;
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wire M0_WVALID;
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wire M0_WREADY;
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wire M0_WREADY;
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wire [`ID_BITS-1:0] M0_BID;
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wire [`ID_BITS-1:0] M0_BID;
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wire [1:0] M0_BRESP;
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wire [1:0] M0_BRESP;
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wire M0_BVALID;
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wire M0_BVALID;
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wire M0_BREADY;
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wire M0_BREADY;
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wire [`ID_BITS-1:0] M0_ARID;
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wire [`ID_BITS-1:0] M0_ARID;
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wire [32-1:0] M0_ARADDR;
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wire [32-1:0] M0_ARADDR;
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wire [`LEN_BITS-1:0] M0_ARLEN;
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wire [`LEN_BITS-1:0] M0_ARLEN;
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wire [`SIZE_BITS-1:0] M0_ARSIZE;
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wire [`SIZE_BITS-1:0] M0_ARSIZE;
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wire M0_ARVALID;
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wire M0_ARVALID;
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wire M0_ARREADY;
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wire M0_ARREADY;
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wire [`ID_BITS-1:0] M0_RID;
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wire [`ID_BITS-1:0] M0_RID;
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wire [64-1:0] M0_RDATA;
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wire [64-1:0] M0_RDATA;
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wire [1:0] M0_RRESP;
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wire [1:0] M0_RRESP;
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wire M0_RLAST;
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wire M0_RLAST;
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wire M0_RVALID;
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wire M0_RVALID;
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wire M0_RREADY;
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wire M0_RREADY;
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wire [31:1] periph_tx_req;
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wire [31:1] periph_tx_req;
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wire [31:1] periph_rx_req;
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wire [31:1] periph_rx_req;
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wire [31:1] periph_tx_clr;
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wire [31:1] periph_tx_clr;
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wire [31:1] periph_rx_clr;
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wire [31:1] periph_rx_clr;
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assign AWID0 = M0_AWID;
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assign AWID0 = M0_AWID;
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assign AWADDR0 = M0_AWADDR;
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assign AWADDR0 = M0_AWADDR;
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assign AWLEN0 = M0_AWLEN;
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assign AWLEN0 = M0_AWLEN;
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assign AWSIZE0 = M0_AWSIZE;
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assign AWSIZE0 = M0_AWSIZE;
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assign AWVALID0 = M0_AWVALID;
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assign AWVALID0 = M0_AWVALID;
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assign WID0 = M0_WID;
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assign WID0 = M0_WID;
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assign WDATA0 = M0_WDATA;
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assign WDATA0 = M0_WDATA;
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assign WSTRB0 = M0_WSTRB;
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assign WSTRB0 = M0_WSTRB;
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assign WLAST0 = M0_WLAST;
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assign WLAST0 = M0_WLAST;
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assign WVALID0 = M0_WVALID;
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assign WVALID0 = M0_WVALID;
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assign BREADY0 = M0_BREADY;
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assign BREADY0 = M0_BREADY;
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assign ARID0 = M0_ARID;
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assign ARID0 = M0_ARID;
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assign ARADDR0 = M0_ARADDR;
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assign ARADDR0 = M0_ARADDR;
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assign ARLEN0 = M0_ARLEN;
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assign ARLEN0 = M0_ARLEN;
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assign ARSIZE0 = M0_ARSIZE;
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assign ARSIZE0 = M0_ARSIZE;
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assign ARVALID0 = M0_ARVALID;
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assign ARVALID0 = M0_ARVALID;
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assign RREADY0 = M0_RREADY;
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assign RREADY0 = M0_RREADY;
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assign M0_AWREADY = AWREADY0;
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assign M0_AWREADY = AWREADY0;
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assign M0_WREADY = WREADY0;
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assign M0_WREADY = WREADY0;
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assign M0_BID = BID0;
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assign M0_BID = BID0;
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assign M0_BRESP = BRESP0;
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assign M0_BRESP = BRESP0;
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assign M0_BVALID = BVALID0;
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assign M0_BVALID = BVALID0;
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assign M0_ARREADY = ARREADY0;
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assign M0_ARREADY = ARREADY0;
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assign M0_RID = RID0;
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assign M0_RID = RID0;
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assign M0_RDATA = RDATA0;
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assign M0_RDATA = RDATA0;
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assign M0_RRESP = RRESP0;
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assign M0_RRESP = RRESP0;
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assign M0_RLAST = RLAST0;
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assign M0_RLAST = RLAST0;
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assign M0_RVALID = RVALID0;
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assign M0_RVALID = RVALID0;
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dma_axi64_dual_core
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dma_axi64_dual_core
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dma_axi64_dual_core (
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dma_axi64_dual_core (
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.clk(clk),
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.clk(clk),
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.reset(reset),
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.reset(reset),
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.scan_en(scan_en),
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.scan_en(scan_en),
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.idle(idle),
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.idle(idle),
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.INT(INT),
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.INT(INT),
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.periph_tx_req(periph_tx_req),
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.periph_tx_req(periph_tx_req),
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.periph_tx_clr(periph_tx_clr),
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.periph_tx_clr(periph_tx_clr),
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.periph_rx_req(periph_rx_req),
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.periph_rx_req(periph_rx_req),
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.periph_rx_clr(periph_rx_clr),
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.periph_rx_clr(periph_rx_clr),
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.pclken(pclken),
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.pclken(pclken),
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.psel(psel),
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.psel(psel),
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.penable(penable),
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.penable(penable),
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.paddr(paddr),
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.paddr(paddr),
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.pwrite(pwrite),
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.pwrite(pwrite),
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.pwdata(pwdata),
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.pwdata(pwdata),
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.prdata(prdata),
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.prdata(prdata),
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.pslverr(pslverr),
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.pslverr(pslverr),
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.pready(pready),
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.pready(pready),
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.rd_port_num0(rd_port_num0),
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.rd_port_num0(rd_port_num0),
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.wr_port_num0(wr_port_num0),
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.wr_port_num0(wr_port_num0),
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.rd_port_num1(rd_port_num1),
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.rd_port_num1(rd_port_num1),
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.wr_port_num1(wr_port_num1),
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.wr_port_num1(wr_port_num1),
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.M0_AWID(M0_AWID),
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.M0_AWID(M0_AWID),
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.M0_AWADDR(M0_AWADDR),
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.M0_AWADDR(M0_AWADDR),
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.M0_AWLEN(M0_AWLEN),
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.M0_AWLEN(M0_AWLEN),
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.M0_AWSIZE(M0_AWSIZE),
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.M0_AWSIZE(M0_AWSIZE),
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.M0_AWVALID(M0_AWVALID),
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.M0_AWVALID(M0_AWVALID),
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.M0_AWREADY(M0_AWREADY),
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.M0_AWREADY(M0_AWREADY),
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.M0_WID(M0_WID),
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.M0_WID(M0_WID),
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.M0_WDATA(M0_WDATA),
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.M0_WDATA(M0_WDATA),
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.M0_WSTRB(M0_WSTRB),
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.M0_WSTRB(M0_WSTRB),
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.M0_WLAST(M0_WLAST),
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.M0_WLAST(M0_WLAST),
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.M0_WVALID(M0_WVALID),
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.M0_WVALID(M0_WVALID),
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.M0_WREADY(M0_WREADY),
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.M0_WREADY(M0_WREADY),
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.M0_BID(M0_BID),
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.M0_BID(M0_BID),
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.M0_BRESP(M0_BRESP),
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.M0_BRESP(M0_BRESP),
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.M0_BVALID(M0_BVALID),
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.M0_BVALID(M0_BVALID),
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.M0_BREADY(M0_BREADY),
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.M0_BREADY(M0_BREADY),
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.M0_ARID(M0_ARID),
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.M0_ARID(M0_ARID),
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.M0_ARADDR(M0_ARADDR),
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.M0_ARADDR(M0_ARADDR),
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.M0_ARLEN(M0_ARLEN),
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.M0_ARLEN(M0_ARLEN),
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.M0_ARSIZE(M0_ARSIZE),
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.M0_ARSIZE(M0_ARSIZE),
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.M0_ARVALID(M0_ARVALID),
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.M0_ARVALID(M0_ARVALID),
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.M0_ARREADY(M0_ARREADY),
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.M0_ARREADY(M0_ARREADY),
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.M0_RID(M0_RID),
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.M0_RID(M0_RID),
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.M0_RDATA(M0_RDATA),
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.M0_RDATA(M0_RDATA),
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.M0_RRESP(M0_RRESP),
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.M0_RRESP(M0_RRESP),
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.M0_RLAST(M0_RLAST),
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.M0_RLAST(M0_RLAST),
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.M0_RVALID(M0_RVALID),
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.M0_RVALID(M0_RVALID),
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.M0_RREADY(M0_RREADY)
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.M0_RREADY(M0_RREADY)
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);
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);
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endmodule
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endmodule
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