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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Author: Eyal Hochberg ////
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//// eyal@provartec.com ////
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//// ////
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//// Downloaded from: http://www.opencores.org ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2010 Provartec LTD ////
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//// www.provartec.com ////
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//// info@provartec.com ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation.////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more////
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//// details. http://www.gnu.org/licenses/lgpl.html ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//---------------------------------------------------------
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//---------------------------------------------------------
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//-- File generated by RobustVerilog parser
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//-- File generated by RobustVerilog parser
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//-- Version: 1.0
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//-- Version: 1.0
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//-- Invoked Fri Mar 25 23:36:55 2011
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//-- Invoked Fri Mar 25 23:36:55 2011
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//--
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//--
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//-- Source file: dma_core_axim_resp.v
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//-- Source file: dma_core_axim_resp.v
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//---------------------------------------------------------
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//---------------------------------------------------------
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module dma_axi64_core0_axim_resp(clk,reset,slverr,decerr,clr,clr_last,ch_num_resp,resp_full,AID,AVALID,AREADY,RESP,ID,VALID,READY,LAST);
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module dma_axi64_core0_axim_resp(clk,reset,slverr,decerr,clr,clr_last,ch_num_resp,resp_full,AID,AVALID,AREADY,RESP,ID,VALID,READY,LAST);
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parameter CMD_DEPTH = 8;
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parameter CMD_DEPTH = 8;
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input clk;
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input clk;
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input reset;
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input reset;
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output slverr;
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output slverr;
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output decerr;
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output decerr;
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output clr;
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output clr;
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output clr_last;
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output clr_last;
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output [2:0] ch_num_resp;
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output [2:0] ch_num_resp;
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output resp_full;
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output resp_full;
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input [`CMD_BITS-1:0] AID;
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input [`CMD_BITS-1:0] AID;
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input AVALID;
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input AVALID;
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input AREADY;
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input AREADY;
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input [1:0] RESP;
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input [1:0] RESP;
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output [`CMD_BITS-1:0] ID;
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output [`CMD_BITS-1:0] ID;
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input VALID;
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input VALID;
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input READY;
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input READY;
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input LAST;
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input LAST;
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parameter RESP_SLVERR = 2'b10;
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parameter RESP_SLVERR = 2'b10;
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parameter RESP_DECERR = 2'b11;
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parameter RESP_DECERR = 2'b11;
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wire clr_pre;
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wire clr_pre;
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wire [2:0] ch_num_resp_pre;
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wire [2:0] ch_num_resp_pre;
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wire clr_last_pre;
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wire clr_last_pre;
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wire slverr_pre;
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wire slverr_pre;
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wire decerr_pre;
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wire decerr_pre;
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reg [2:0] ch_num_resp;
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reg [2:0] ch_num_resp;
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wire resp_push;
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wire resp_push;
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wire resp_pop;
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wire resp_pop;
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wire resp_empty;
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wire resp_empty;
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wire resp_full;
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wire resp_full;
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wire [`CMD_BITS-1:0] ID;
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wire [`CMD_BITS-1:0] ID;
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assign resp_push = AVALID & AREADY;
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assign resp_push = AVALID & AREADY;
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assign resp_pop = VALID & READY & LAST;
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assign resp_pop = VALID & READY & LAST;
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assign clr_pre = resp_pop;
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assign clr_pre = resp_pop;
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assign ch_num_resp_pre = ID[2:0] ;
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assign ch_num_resp_pre = ID[2:0] ;
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assign slverr_pre = clr_pre & RESP == RESP_SLVERR;
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assign slverr_pre = clr_pre & RESP == RESP_SLVERR;
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assign decerr_pre = clr_pre & RESP == RESP_DECERR;
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assign decerr_pre = clr_pre & RESP == RESP_DECERR;
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assign clr_last_pre = clr_pre & ID[3];
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assign clr_last_pre = clr_pre & ID[3];
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prgen_delay #(1) delay_clr(.clk(clk), .reset(reset), .din(clr_pre), .dout(clr));
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prgen_delay #(1) delay_clr(.clk(clk), .reset(reset), .din(clr_pre), .dout(clr));
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prgen_delay #(1) delay_clr_last(.clk(clk), .reset(reset), .din(clr_last_pre), .dout(clr_last));
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prgen_delay #(1) delay_clr_last(.clk(clk), .reset(reset), .din(clr_last_pre), .dout(clr_last));
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prgen_delay #(1) delay_slverr(.clk(clk), .reset(reset), .din(slverr_pre), .dout(slverr));
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prgen_delay #(1) delay_slverr(.clk(clk), .reset(reset), .din(slverr_pre), .dout(slverr));
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prgen_delay #(1) delay_decerr(.clk(clk), .reset(reset), .din(decerr_pre), .dout(decerr));
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prgen_delay #(1) delay_decerr(.clk(clk), .reset(reset), .din(decerr_pre), .dout(decerr));
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always @(posedge clk or posedge reset)
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always @(posedge clk or posedge reset)
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if (reset)
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if (reset)
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ch_num_resp <= #1 3'b000;
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ch_num_resp <= #1 3'b000;
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else if (clr_pre)
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else if (clr_pre)
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ch_num_resp <= #1 ch_num_resp_pre;
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ch_num_resp <= #1 ch_num_resp_pre;
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prgen_fifo #(`CMD_BITS, CMD_DEPTH)
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prgen_fifo #(`CMD_BITS, CMD_DEPTH)
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resp_fifo(
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resp_fifo(
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.clk(clk),
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.clk(clk),
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.reset(reset),
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.reset(reset),
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.push(resp_push),
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.push(resp_push),
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.pop(resp_pop),
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.pop(resp_pop),
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.din(AID),
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.din(AID),
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.dout(ID),
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.dout(ID),
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.empty(resp_empty),
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.empty(resp_empty),
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.full(resp_full)
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.full(resp_full)
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);
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);
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endmodule
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endmodule
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