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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Author: Eyal Hochberg ////
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//// eyal@provartec.com ////
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//// ////
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//// Downloaded from: http://www.opencores.org ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2010 Provartec LTD ////
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//// www.provartec.com ////
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//// info@provartec.com ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation.////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more////
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//// details. http://www.gnu.org/licenses/lgpl.html ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//---------------------------------------------------------
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//---------------------------------------------------------
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//-- File generated by RobustVerilog parser
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//-- File generated by RobustVerilog parser
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//-- Version: 1.0
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//-- Version: 1.0
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//-- Invoked Fri Mar 25 23:36:54 2011
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//-- Invoked Fri Mar 25 23:36:54 2011
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//--
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//--
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//-- Source file: dma_core_axim_wdata.v
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//-- Source file: dma_core_axim_wdata.v
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//---------------------------------------------------------
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//---------------------------------------------------------
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module dma_axi64_core0_axim_wdata(clk,reset,rd_transfer,rd_transfer_size,ch_fifo_rd,ch_fifo_rsize,ch_fifo_rdata,ch_fifo_rd_valid,ch_fifo_wr_ready,ch_fifo_rd_num,wr_transfer_num,wr_transfer,wr_transfer_size,wr_next_size,wr_resp_full,wr_cmd_full,wr_clr_line,wr_clr_line_num,joint_stall,axim_timeout_num,axim_timeout,AWID,AWADDR,AWLEN,AWSIZE,AWVALID,AWREADY,AJOINT,WDATA,WSTRB,WLAST,WVALID,WREADY);
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module dma_axi64_core0_axim_wdata(clk,reset,rd_transfer,rd_transfer_size,ch_fifo_rd,ch_fifo_rsize,ch_fifo_rdata,ch_fifo_rd_valid,ch_fifo_wr_ready,ch_fifo_rd_num,wr_transfer_num,wr_transfer,wr_transfer_size,wr_next_size,wr_resp_full,wr_cmd_full,wr_clr_line,wr_clr_line_num,joint_stall,axim_timeout_num,axim_timeout,AWID,AWADDR,AWLEN,AWSIZE,AWVALID,AWREADY,AJOINT,WDATA,WSTRB,WLAST,WVALID,WREADY);
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input clk;
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input clk;
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input reset;
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input reset;
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input rd_transfer;
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input rd_transfer;
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input [4-1:0] rd_transfer_size;
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input [4-1:0] rd_transfer_size;
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output ch_fifo_rd;
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output ch_fifo_rd;
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output [4-1:0] ch_fifo_rsize;
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output [4-1:0] ch_fifo_rsize;
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input [64-1:0] ch_fifo_rdata;
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input [64-1:0] ch_fifo_rdata;
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input ch_fifo_rd_valid;
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input ch_fifo_rd_valid;
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input ch_fifo_wr_ready;
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input ch_fifo_wr_ready;
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output [2:0] ch_fifo_rd_num;
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output [2:0] ch_fifo_rd_num;
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output [2:0] wr_transfer_num;
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output [2:0] wr_transfer_num;
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output wr_transfer;
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output wr_transfer;
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output [4-1:0] wr_transfer_size;
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output [4-1:0] wr_transfer_size;
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output [4-1:0] wr_next_size;
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output [4-1:0] wr_next_size;
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input wr_resp_full;
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input wr_resp_full;
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output wr_cmd_full;
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output wr_cmd_full;
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output wr_clr_line;
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output wr_clr_line;
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output [2:0] wr_clr_line_num;
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output [2:0] wr_clr_line_num;
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output joint_stall;
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output joint_stall;
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output [2:0] axim_timeout_num;
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output [2:0] axim_timeout_num;
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output axim_timeout;
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output axim_timeout;
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input [`CMD_BITS-1:0] AWID;
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input [`CMD_BITS-1:0] AWID;
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input [32-1:0] AWADDR;
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input [32-1:0] AWADDR;
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input [`LEN_BITS-1:0] AWLEN;
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input [`LEN_BITS-1:0] AWLEN;
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input [1:0] AWSIZE;
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input [1:0] AWSIZE;
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input AWVALID;
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input AWVALID;
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input AWREADY;
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input AWREADY;
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input AJOINT;
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input AJOINT;
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output [64-1:0] WDATA;
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output [64-1:0] WDATA;
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output [8-1:0] WSTRB;
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output [8-1:0] WSTRB;
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output WLAST;
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output WLAST;
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output WVALID;
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output WVALID;
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input WREADY;
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input WREADY;
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wire [`CMD_BITS-1:0] WID;
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wire [`CMD_BITS-1:0] WID;
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wire [`CMD_BITS-1:0] WID_pre;
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wire [`CMD_BITS-1:0] WID_pre;
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reg [8-1:0] WSTRB_pre;
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reg [8-1:0] WSTRB_pre;
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wire [1:0] WSIZE_pre;
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wire [1:0] WSIZE_pre;
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wire [`LEN_BITS-1:0] WLEN_pre;
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wire [`LEN_BITS-1:0] WLEN_pre;
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wire [`CMD_BITS-1:0] WID_data;
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wire [`CMD_BITS-1:0] WID_data;
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wire [8-1:0] WSTRB_data;
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wire [8-1:0] WSTRB_data;
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wire [1:0] WSIZE_data;
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wire [1:0] WSIZE_data;
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wire [`LEN_BITS-1:0] WLEN_data;
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wire [`LEN_BITS-1:0] WLEN_data;
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wire WVALID;
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wire WVALID;
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wire WLAST;
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wire WLAST;
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wire valid_last;
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wire valid_last;
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wire wr_clr_line_stall_pre;
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wire wr_clr_line_stall_pre;
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wire wr_clr_line_stall;
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wire wr_clr_line_stall;
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wire wr_clr_line_pre;
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wire wr_clr_line_pre;
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reg [2:0] wr_clr_line_num;
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reg [2:0] wr_clr_line_num;
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wire [2:0] wr_transfer_num_pre;
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wire [2:0] wr_transfer_num_pre;
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wire wr_transfer_pre;
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wire wr_transfer_pre;
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wire [4-1:0] wr_transfer_size_pre;
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wire [4-1:0] wr_transfer_size_pre;
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reg [2:0] wr_transfer_num;
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reg [2:0] wr_transfer_num;
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wire wr_transfer;
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wire wr_transfer;
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reg [4-1:0] wr_transfer_size;
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reg [4-1:0] wr_transfer_size;
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reg [2:0] last_channel;
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reg [2:0] last_channel;
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wire [`CMD_BITS-1:0] WID_cmd;
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wire [`CMD_BITS-1:0] WID_cmd;
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wire [1:0] WSIZE_cmd;
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wire [1:0] WSIZE_cmd;
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reg [4-1:0] wr_next_size;
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reg [4-1:0] wr_next_size;
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wire [`LEN_BITS-1:0] WLEN_cmd;
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wire [`LEN_BITS-1:0] WLEN_cmd;
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wire data_ready;
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wire data_ready;
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wire [2:0] data_fullness_pre;
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wire [2:0] data_fullness_pre;
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reg [2:0] data_fullness;
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reg [2:0] data_fullness;
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wire joint_fifo_rd_valid;
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wire joint_fifo_rd_valid;
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wire joint_req_out;
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wire joint_req_out;
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wire joint_stall;
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wire joint_stall;
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wire rd_transfer_joint;
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wire rd_transfer_joint;
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wire [4-1:0] rd_transfer_size_joint;
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wire [4-1:0] rd_transfer_size_joint;
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wire rd_transfer_full;
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wire rd_transfer_full;
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wire cmd_push;
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wire cmd_push;
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wire cmd_pop;
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wire cmd_pop;
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wire cmd_pop_d;
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wire cmd_pop_d;
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wire cmd_empty;
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wire cmd_empty;
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wire cmd_full;
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wire cmd_full;
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wire cmd_data_push;
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wire cmd_data_push;
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wire cmd_data_pop;
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wire cmd_data_pop;
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wire cmd_data_empty;
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wire cmd_data_empty;
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wire cmd_data_full;
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wire cmd_data_full;
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wire data_push;
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wire data_push;
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wire data_pop;
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wire data_pop;
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wire data_empty;
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wire data_empty;
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wire data_full;
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wire data_full;
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reg [`LEN_BITS-1:0] rd_out_count;
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reg [`LEN_BITS-1:0] rd_out_count;
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reg [`LEN_BITS-1:0] rd_in_count;
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reg [`LEN_BITS-1:0] rd_in_count;
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wire data_pending_pre;
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wire data_pending_pre;
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wire data_pending;
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wire data_pending;
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wire line_end;
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wire line_end;
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wire [2:0] line_end_num;
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wire [2:0] line_end_num;
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//joint
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//joint
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assign data_ready = ch_fifo_rd_valid;
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assign data_ready = ch_fifo_rd_valid;
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assign data_fullness_pre = data_fullness + data_ready - wr_transfer_pre;
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assign data_fullness_pre = data_fullness + data_ready - wr_transfer_pre;
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always @(posedge clk or posedge reset)
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always @(posedge clk or posedge reset)
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if (reset)
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if (reset)
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data_fullness <= #1 3'd0;
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data_fullness <= #1 3'd0;
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else if (data_ready | wr_transfer_pre)
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else if (data_ready | wr_transfer_pre)
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data_fullness <= #1 data_fullness_pre;
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data_fullness <= #1 data_fullness_pre;
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prgen_joint_stall #(4)
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prgen_joint_stall #(4)
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gen_joint_stall (
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gen_joint_stall (
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.clk(clk),
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.clk(clk),
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.reset(reset),
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.reset(reset),
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.joint_req_out(joint_req_out),
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.joint_req_out(joint_req_out),
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.rd_transfer(rd_transfer),
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.rd_transfer(rd_transfer),
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.rd_transfer_size(rd_transfer_size),
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.rd_transfer_size(rd_transfer_size),
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.ch_fifo_rd(ch_fifo_rd),
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.ch_fifo_rd(ch_fifo_rd),
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.data_fullness_pre(data_fullness_pre),
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.data_fullness_pre(data_fullness_pre),
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.HOLD(1'b0),
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.HOLD(1'b0),
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.joint_fifo_rd_valid(joint_fifo_rd_valid),
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.joint_fifo_rd_valid(joint_fifo_rd_valid),
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.rd_transfer_size_joint(rd_transfer_size_joint),
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.rd_transfer_size_joint(rd_transfer_size_joint),
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.rd_transfer_full(rd_transfer_full),
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.rd_transfer_full(rd_transfer_full),
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.joint_stall(joint_stall)
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.joint_stall(joint_stall)
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);
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);
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//fifo rd command
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//fifo rd command
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assign data_pending_pre = WVALID & (~WREADY);
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assign data_pending_pre = WVALID & (~WREADY);
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prgen_delay #(1) delay_pending (.clk(clk), .reset(reset), .din(data_pending_pre), .dout(data_pending));
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prgen_delay #(1) delay_pending (.clk(clk), .reset(reset), .din(data_pending_pre), .dout(data_pending));
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//assign wr_next_size = 1'b1 << WSIZE_cmd;
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//assign wr_next_size = 1'b1 << WSIZE_cmd;
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always @(/*AUTOSENSE*/WSIZE_cmd)
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always @(/*AUTOSENSE*/WSIZE_cmd)
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begin
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begin
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case (WSIZE_cmd)
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case (WSIZE_cmd)
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2'b00 : wr_next_size = 4'd1;
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2'b00 : wr_next_size = 4'd1;
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2'b01 : wr_next_size = 4'd2;
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2'b01 : wr_next_size = 4'd2;
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2'b10 : wr_next_size = 4'd4;
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2'b10 : wr_next_size = 4'd4;
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2'b11 : wr_next_size = 4'd8;
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2'b11 : wr_next_size = 4'd8;
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endcase
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endcase
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end
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end
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assign ch_fifo_rd =
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assign ch_fifo_rd =
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joint_fifo_rd_valid |
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joint_fifo_rd_valid |
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((~cmd_empty) &
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((~cmd_empty) &
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(~data_pending) &
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(~data_pending) &
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(~wr_clr_line_stall) &
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(~wr_clr_line_stall) &
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ch_fifo_wr_ready);
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ch_fifo_wr_ready);
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assign ch_fifo_rsize =
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assign ch_fifo_rsize =
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joint_fifo_rd_valid ? rd_transfer_size_joint :
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joint_fifo_rd_valid ? rd_transfer_size_joint :
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WID_cmd[5:4] == 2'b00 ? 4'd1 :
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WID_cmd[5:4] == 2'b00 ? 4'd1 :
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WID_cmd[5:4] == 2'b01 ? 4'd2 :
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WID_cmd[5:4] == 2'b01 ? 4'd2 :
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WID_cmd[5:4] == 2'b10 ? 4'd4 : 4'd8;
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WID_cmd[5:4] == 2'b10 ? 4'd4 : 4'd8;
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assign ch_fifo_rd_num = WID_cmd[2:0];
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assign ch_fifo_rd_num = WID_cmd[2:0];
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prgen_delay #(1) delay_cmd_pop (.clk(clk), .reset(reset), .din(cmd_pop), .dout(cmd_pop_d));
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prgen_delay #(1) delay_cmd_pop (.clk(clk), .reset(reset), .din(cmd_pop), .dout(cmd_pop_d));
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always @(posedge clk or posedge reset)
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always @(posedge clk or posedge reset)
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if (reset)
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if (reset)
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last_channel <= #1 3'b000;
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last_channel <= #1 3'b000;
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else if (cmd_push)
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else if (cmd_push)
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last_channel <= #1 WID_pre[2:0];
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last_channel <= #1 WID_pre[2:0];
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//update pointers in channel
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//update pointers in channel
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assign wr_transfer_num_pre = WID_data[2:0];
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assign wr_transfer_num_pre = WID_data[2:0];
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assign wr_transfer_pre = WVALID & WREADY;
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assign wr_transfer_pre = WVALID & WREADY;
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assign wr_transfer_size_pre =
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assign wr_transfer_size_pre =
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WID_data[5:4] == 2'b00 ? 4'd1 :
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WID_data[5:4] == 2'b00 ? 4'd1 :
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WID_data[5:4] == 2'b01 ? 4'd2 :
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WID_data[5:4] == 2'b01 ? 4'd2 :
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WID_data[5:4] == 2'b10 ? 4'd4 : 4'd8;
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WID_data[5:4] == 2'b10 ? 4'd4 : 4'd8;
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prgen_delay #(1) delay_wr_transfer (.clk(clk), .reset(reset), .din(wr_transfer_pre), .dout(wr_transfer));
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prgen_delay #(1) delay_wr_transfer (.clk(clk), .reset(reset), .din(wr_transfer_pre), .dout(wr_transfer));
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always @(posedge clk or posedge reset)
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always @(posedge clk or posedge reset)
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if (reset)
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if (reset)
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begin
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begin
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wr_transfer_num <= #1 3'd0;
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wr_transfer_num <= #1 3'd0;
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wr_transfer_size <= #1 3'd0;
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wr_transfer_size <= #1 3'd0;
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end
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end
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else if (wr_transfer_pre)
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else if (wr_transfer_pre)
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begin
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begin
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wr_transfer_num <= #1 wr_transfer_num_pre;
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wr_transfer_num <= #1 wr_transfer_num_pre;
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wr_transfer_size <= #1 wr_transfer_size_pre;
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wr_transfer_size <= #1 wr_transfer_size_pre;
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end
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end
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assign valid_last = ch_fifo_rd & (rd_out_count == WLEN_cmd) & (~cmd_empty);
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assign valid_last = ch_fifo_rd & (rd_out_count == WLEN_cmd) & (~cmd_empty);
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assign wr_clr_line_pre = valid_last & line_end;
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assign wr_clr_line_pre = valid_last & line_end;
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always @(posedge clk or posedge reset)
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always @(posedge clk or posedge reset)
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if (reset)
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if (reset)
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wr_clr_line_num <= #1 3'd0;
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wr_clr_line_num <= #1 3'd0;
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else if (wr_clr_line_pre)
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else if (wr_clr_line_pre)
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wr_clr_line_num <= #1 line_end_num;
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wr_clr_line_num <= #1 line_end_num;
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assign wr_clr_line_stall_pre = wr_clr_line_pre & (ch_fifo_rd_num == line_end_num);
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assign wr_clr_line_stall_pre = wr_clr_line_pre & (ch_fifo_rd_num == line_end_num);
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prgen_delay #(1) delay_stall (.clk(clk), .reset(reset), .din(wr_clr_line_stall_pre), .dout(wr_clr_line_stall));
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prgen_delay #(1) delay_stall (.clk(clk), .reset(reset), .din(wr_clr_line_stall_pre), .dout(wr_clr_line_stall));
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prgen_delay #(2) delay_clr_line (.clk(clk), .reset(reset), .din(wr_clr_line_pre), .dout(wr_clr_line));
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prgen_delay #(2) delay_clr_line (.clk(clk), .reset(reset), .din(wr_clr_line_pre), .dout(wr_clr_line));
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//command phase
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//command phase
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assign wr_cmd_full = cmd_full | cmd_data_full | wr_resp_full;
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assign wr_cmd_full = cmd_full | cmd_data_full | wr_resp_full;
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assign cmd_push = AWVALID & AWREADY;
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assign cmd_push = AWVALID & AWREADY;
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assign cmd_pop = valid_last;
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assign cmd_pop = valid_last;
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assign WID_pre = AWID;
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assign WID_pre = AWID;
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assign WLEN_pre = AWLEN;
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assign WLEN_pre = AWLEN;
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assign WSIZE_pre = AWSIZE;
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assign WSIZE_pre = AWSIZE;
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//always @(/*AUTOSENSE*/ - no AUTOSENSE due to defines
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//always @(/*AUTOSENSE*/ - no AUTOSENSE due to defines
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always @(AWADDR or AWSIZE)
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always @(AWADDR or AWSIZE)
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begin
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begin
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case ({AWSIZE[1:0], AWADDR[2:0]})
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case ({AWSIZE[1:0], AWADDR[2:0]})
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//8 bit
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//8 bit
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{2'b00, 3'b000} : WSTRB_pre = 8'b0000_0001;
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{2'b00, 3'b000} : WSTRB_pre = 8'b0000_0001;
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{2'b00, 3'b001} : WSTRB_pre = 8'b0000_0010;
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{2'b00, 3'b001} : WSTRB_pre = 8'b0000_0010;
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{2'b00, 3'b010} : WSTRB_pre = 8'b0000_0100;
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{2'b00, 3'b010} : WSTRB_pre = 8'b0000_0100;
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{2'b00, 3'b011} : WSTRB_pre = 8'b0000_1000;
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{2'b00, 3'b011} : WSTRB_pre = 8'b0000_1000;
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{2'b00, 3'b100} : WSTRB_pre = 8'b0001_0000;
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{2'b00, 3'b100} : WSTRB_pre = 8'b0001_0000;
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{2'b00, 3'b101} : WSTRB_pre = 8'b0010_0000;
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{2'b00, 3'b101} : WSTRB_pre = 8'b0010_0000;
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{2'b00, 3'b110} : WSTRB_pre = 8'b0100_0000;
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{2'b00, 3'b110} : WSTRB_pre = 8'b0100_0000;
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{2'b00, 3'b111} : WSTRB_pre = 8'b1000_0000;
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{2'b00, 3'b111} : WSTRB_pre = 8'b1000_0000;
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//16 bit
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//16 bit
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{2'b01, 3'b000} : WSTRB_pre = 8'b0000_0011;
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{2'b01, 3'b000} : WSTRB_pre = 8'b0000_0011;
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//{2'b01, 3'b001} : WSTRB_pre = 8'b0000_0011;
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//{2'b01, 3'b001} : WSTRB_pre = 8'b0000_0011;
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{2'b01, 3'b010} : WSTRB_pre = 8'b0000_1100;
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{2'b01, 3'b010} : WSTRB_pre = 8'b0000_1100;
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//{2'b01, 3'b011} : WSTRB_pre = 8'b0000_1100;
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//{2'b01, 3'b011} : WSTRB_pre = 8'b0000_1100;
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{2'b01, 3'b100} : WSTRB_pre = 8'b0011_0000;
|
{2'b01, 3'b100} : WSTRB_pre = 8'b0011_0000;
|
//{2'b01, 3'b101} : WSTRB_pre = 8'b0011_0000;
|
//{2'b01, 3'b101} : WSTRB_pre = 8'b0011_0000;
|
{2'b01, 3'b110} : WSTRB_pre = 8'b1100_0000;
|
{2'b01, 3'b110} : WSTRB_pre = 8'b1100_0000;
|
//{2'b01, 3'b111} : WSTRB_pre = 8'b1100_0000;
|
//{2'b01, 3'b111} : WSTRB_pre = 8'b1100_0000;
|
|
|
//32 bit
|
//32 bit
|
{2'b10, 3'b000} : WSTRB_pre = 8'b0000_1111;
|
{2'b10, 3'b000} : WSTRB_pre = 8'b0000_1111;
|
//{2'b10, 3'b001} : WSTRB_pre = 8'b0000_1111;
|
//{2'b10, 3'b001} : WSTRB_pre = 8'b0000_1111;
|
//{2'b10, 3'b010} : WSTRB_pre = 8'b0000_1111;
|
//{2'b10, 3'b010} : WSTRB_pre = 8'b0000_1111;
|
//{2'b10, 3'b011} : WSTRB_pre = 8'b0000_1111;
|
//{2'b10, 3'b011} : WSTRB_pre = 8'b0000_1111;
|
{2'b10, 3'b100} : WSTRB_pre = 8'b1111_0000;
|
{2'b10, 3'b100} : WSTRB_pre = 8'b1111_0000;
|
//{2'b10, 3'b101} : WSTRB_pre = 8'b1111_0000;
|
//{2'b10, 3'b101} : WSTRB_pre = 8'b1111_0000;
|
//{2'b10, 3'b110} : WSTRB_pre = 8'b1111_0000;
|
//{2'b10, 3'b110} : WSTRB_pre = 8'b1111_0000;
|
//{2'b10, 3'b111} : WSTRB_pre = 8'b1111_0000;
|
//{2'b10, 3'b111} : WSTRB_pre = 8'b1111_0000;
|
|
|
//64 bit
|
//64 bit
|
default : WSTRB_pre = 8'b1111_1111;
|
default : WSTRB_pre = 8'b1111_1111;
|
endcase
|
endcase
|
end
|
end
|
|
|
|
|
prgen_fifo #(`CMD_BITS+`LEN_BITS+2+1, 4)
|
prgen_fifo #(`CMD_BITS+`LEN_BITS+2+1, 4)
|
cmd_fifo(
|
cmd_fifo(
|
.clk(clk),
|
.clk(clk),
|
.reset(reset),
|
.reset(reset),
|
.push(cmd_push),
|
.push(cmd_push),
|
.pop(cmd_pop),
|
.pop(cmd_pop),
|
.din({WID_pre,
|
.din({WID_pre,
|
WSIZE_pre,
|
WSIZE_pre,
|
WLEN_pre,
|
WLEN_pre,
|
AJOINT
|
AJOINT
|
}
|
}
|
),
|
),
|
.dout({WID_cmd,
|
.dout({WID_cmd,
|
WSIZE_cmd,
|
WSIZE_cmd,
|
WLEN_cmd,
|
WLEN_cmd,
|
joint_req_out
|
joint_req_out
|
}
|
}
|
),
|
),
|
.empty(cmd_empty),
|
.empty(cmd_empty),
|
.full(cmd_full)
|
.full(cmd_full)
|
);
|
);
|
|
|
|
|
assign line_end = WID_cmd[6];
|
assign line_end = WID_cmd[6];
|
assign line_end_num = WID_cmd[2:0];
|
assign line_end_num = WID_cmd[2:0];
|
|
|
always @(posedge clk or posedge reset)
|
always @(posedge clk or posedge reset)
|
if (reset)
|
if (reset)
|
rd_out_count <= #1 {`LEN_BITS{1'b0}};
|
rd_out_count <= #1 {`LEN_BITS{1'b0}};
|
else if (cmd_pop)
|
else if (cmd_pop)
|
rd_out_count <= #1 {`LEN_BITS{1'b0}};
|
rd_out_count <= #1 {`LEN_BITS{1'b0}};
|
else if (ch_fifo_rd)
|
else if (ch_fifo_rd)
|
rd_out_count <= #1 rd_out_count + 1'b1;
|
rd_out_count <= #1 rd_out_count + 1'b1;
|
|
|
|
|
//data phase
|
//data phase
|
assign cmd_data_push = cmd_push;
|
assign cmd_data_push = cmd_push;
|
assign cmd_data_pop = WVALID & WREADY & WLAST;
|
assign cmd_data_pop = WVALID & WREADY & WLAST;
|
|
|
assign WSTRB = (rd_in_count[0] ? {WSTRB_data[3:0], WSTRB_data[7:4]} : WSTRB_data) & {8{WVALID}};
|
assign WSTRB = (rd_in_count[0] ? {WSTRB_data[3:0], WSTRB_data[7:4]} : WSTRB_data) & {8{WVALID}};
|
|
|
assign WID = WID_data;
|
assign WID = WID_data;
|
|
|
|
|
|
|
prgen_fifo #(8+`LEN_BITS+`CMD_BITS+2, 4)
|
prgen_fifo #(8+`LEN_BITS+`CMD_BITS+2, 4)
|
cmd_data_fifo(
|
cmd_data_fifo(
|
.clk(clk),
|
.clk(clk),
|
.reset(reset),
|
.reset(reset),
|
.push(cmd_data_push),
|
.push(cmd_data_push),
|
.pop(cmd_data_pop),
|
.pop(cmd_data_pop),
|
.din({WLEN_pre,
|
.din({WLEN_pre,
|
WSIZE_pre,
|
WSIZE_pre,
|
WSTRB_pre,
|
WSTRB_pre,
|
WID_pre
|
WID_pre
|
}),
|
}),
|
.dout({WLEN_data,
|
.dout({WLEN_data,
|
WSIZE_data,
|
WSIZE_data,
|
WSTRB_data,
|
WSTRB_data,
|
WID_data
|
WID_data
|
}),
|
}),
|
.empty(cmd_data_empty),
|
.empty(cmd_data_empty),
|
.full(cmd_data_full)
|
.full(cmd_data_full)
|
);
|
);
|
|
|
|
|
always @(posedge clk or posedge reset)
|
always @(posedge clk or posedge reset)
|
if (reset)
|
if (reset)
|
rd_in_count <= #1 {`LEN_BITS{1'b0}};
|
rd_in_count <= #1 {`LEN_BITS{1'b0}};
|
else if (cmd_data_pop)
|
else if (cmd_data_pop)
|
rd_in_count <= #1 {`LEN_BITS{1'b0}};
|
rd_in_count <= #1 {`LEN_BITS{1'b0}};
|
else if (wr_transfer_pre)
|
else if (wr_transfer_pre)
|
rd_in_count <= #1 rd_in_count + 1'b1;
|
rd_in_count <= #1 rd_in_count + 1'b1;
|
|
|
|
|
|
|
//data fifo
|
//data fifo
|
assign data_push = ch_fifo_rd_valid;
|
assign data_push = ch_fifo_rd_valid;
|
assign data_pop = wr_transfer_pre;
|
assign data_pop = wr_transfer_pre;
|
|
|
|
|
//depth is set by maximum fifo read data latency
|
//depth is set by maximum fifo read data latency
|
prgen_fifo #(64, 5+2)
|
prgen_fifo #(64, 5+2)
|
data_fifo(
|
data_fifo(
|
.clk(clk),
|
.clk(clk),
|
.reset(reset),
|
.reset(reset),
|
.push(data_push),
|
.push(data_push),
|
.pop(data_pop),
|
.pop(data_pop),
|
.din(ch_fifo_rdata),
|
.din(ch_fifo_rdata),
|
.dout(WDATA),
|
.dout(WDATA),
|
.empty(data_empty),
|
.empty(data_empty),
|
.full(data_full)
|
.full(data_full)
|
);
|
);
|
|
|
assign WVALID = ~data_empty;
|
assign WVALID = ~data_empty;
|
|
|
assign WLAST = WVALID & (rd_in_count == WLEN_data) & (~cmd_data_empty);
|
assign WLAST = WVALID & (rd_in_count == WLEN_data) & (~cmd_data_empty);
|
|
|
|
|
|
|
dma_axi64_core0_axim_timeout dma_axi64_axim_timeout (
|
dma_axi64_core0_axim_timeout dma_axi64_axim_timeout (
|
.clk(clk),
|
.clk(clk),
|
.reset(reset),
|
.reset(reset),
|
.VALID(WVALID),
|
.VALID(WVALID),
|
.READY(WREADY),
|
.READY(WREADY),
|
.ID(WID),
|
.ID(WID),
|
.axim_timeout_num(axim_timeout_num),
|
.axim_timeout_num(axim_timeout_num),
|
.axim_timeout(axim_timeout)
|
.axim_timeout(axim_timeout)
|
);
|
);
|
|
|
endmodule
|
endmodule
|
|
|
|
|
|
|
|
|
|
|
|
|