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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Author: Eyal Hochberg ////
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//// eyal@provartec.com ////
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//// ////
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//// Downloaded from: http://www.opencores.org ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2010 Provartec LTD ////
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//// www.provartec.com ////
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//// info@provartec.com ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation.////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more////
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//// details. http://www.gnu.org/licenses/lgpl.html ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//---------------------------------------------------------
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//---------------------------------------------------------
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//-- File generated by RobustVerilog parser
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//-- File generated by RobustVerilog parser
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//-- Version: 1.0
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//-- Version: 1.0
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//-- Invoked Fri Mar 25 23:36:56 2011
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//-- Invoked Fri Mar 25 23:36:56 2011
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//--
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//--
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//-- Source file: dma_ch_calc_size.v
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//-- Source file: dma_ch_calc_size.v
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//---------------------------------------------------------
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//---------------------------------------------------------
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module dma_axi64_core0_ch_calc_size (clk,reset,ch_update,ch_update_d,ch_update_d2,ch_update_d3,ch_end,ch_end_flush,load_in_prog,load_req_in_prog,joint_line_req_clr,wr_cmd_pending,outs_empty,burst_start,burst_addr,burst_max_size,x_remain,fifo_wr_ready,fifo_remain,burst_last,burst_size,burst_ready,joint_ready_in,joint_ready_out,joint,joint_line_req_in,joint_line_req_out,joint_burst_req_in,joint_burst_req_out,page_cross,joint_cross,joint_flush,joint_flush_in);
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module dma_axi64_core0_ch_calc_size (clk,reset,ch_update,ch_update_d,ch_update_d2,ch_update_d3,ch_end,ch_end_flush,load_in_prog,load_req_in_prog,joint_line_req_clr,wr_cmd_pending,outs_empty,burst_start,burst_addr,burst_max_size,x_remain,fifo_wr_ready,fifo_remain,burst_last,burst_size,burst_ready,joint_ready_in,joint_ready_out,joint,joint_line_req_in,joint_line_req_out,joint_burst_req_in,joint_burst_req_out,page_cross,joint_cross,joint_flush,joint_flush_in);
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parameter READ = 0;
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parameter READ = 0;
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input clk;
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input clk;
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input reset;
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input reset;
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input ch_update;
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input ch_update;
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input ch_update_d;
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input ch_update_d;
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input ch_update_d2;
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input ch_update_d2;
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input ch_update_d3;
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input ch_update_d3;
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input ch_end;
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input ch_end;
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input ch_end_flush;
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input ch_end_flush;
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input load_in_prog;
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input load_in_prog;
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input load_req_in_prog;
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input load_req_in_prog;
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input joint_line_req_clr;
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input joint_line_req_clr;
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input wr_cmd_pending;
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input wr_cmd_pending;
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input outs_empty;
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input outs_empty;
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input burst_start;
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input burst_start;
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input [32-1:0] burst_addr;
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input [32-1:0] burst_addr;
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input [8-1:0] burst_max_size;
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input [8-1:0] burst_max_size;
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input [10-1:0] x_remain;
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input [10-1:0] x_remain;
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input fifo_wr_ready;
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input fifo_wr_ready;
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input [5:0] fifo_remain;
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input [5:0] fifo_remain;
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output burst_last;
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output burst_last;
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output [8-1:0] burst_size;
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output [8-1:0] burst_size;
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output burst_ready;
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output burst_ready;
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input joint_ready_in;
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input joint_ready_in;
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output joint_ready_out;
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output joint_ready_out;
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input joint;
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input joint;
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input joint_line_req_in;
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input joint_line_req_in;
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output joint_line_req_out;
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output joint_line_req_out;
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input joint_burst_req_in;
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input joint_burst_req_in;
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output joint_burst_req_out;
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output joint_burst_req_out;
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input page_cross;
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input page_cross;
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input joint_cross;
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input joint_cross;
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output joint_flush;
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output joint_flush;
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input joint_flush_in;
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input joint_flush_in;
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parameter CMD_SIZE = 16; //4*32 bit
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parameter CMD_SIZE = 16; //4*32 bit
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wire [8-1:0] burst_size_pre;
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wire [8-1:0] burst_size_pre;
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wire [8-1:0] x_remain_fifo;
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wire [8-1:0] x_remain_fifo;
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wire [8-1:0] max_burst_align;
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wire [8-1:0] max_burst_align;
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wire [8-1:0] burst_size_pre2;
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wire [8-1:0] burst_size_pre2;
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reg [8-1:0] burst_size;
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reg [8-1:0] burst_size;
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reg burst_ready;
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reg burst_ready;
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wire fifo_not_ready_pre;
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wire fifo_not_ready_pre;
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wire fifo_not_ready;
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wire fifo_not_ready;
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wire joint_update;
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wire joint_update;
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wire joint_ready_out;
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wire joint_ready_out;
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wire joint_line_req_out;
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wire joint_line_req_out;
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wire joint_burst_req_out;
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wire joint_burst_req_out;
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wire joint_wait;
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wire joint_wait;
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reg [1:0] joint_burst_req_reg;
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reg [1:0] joint_burst_req_reg;
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wire [1:0] joint_burst_req;
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wire [1:0] joint_burst_req;
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wire [8-1:0] joint_burst_req_size;
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wire [8-1:0] joint_burst_req_size;
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reg joint_line_req_reg;
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reg joint_line_req_reg;
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wire joint_line_req;
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wire joint_line_req;
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wire [8-1:0] joint_line_req_size;
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wire [8-1:0] joint_line_req_size;
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wire joint_buffer_small;
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wire joint_buffer_small;
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wire release_fifo;
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wire release_fifo;
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assign x_remain_fifo = |x_remain[10-1:8] ? {1'b1, {8-1{1'b0}}} : x_remain[8-1:0];
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assign x_remain_fifo = |x_remain[10-1:8] ? {1'b1, {8-1{1'b0}}} : x_remain[8-1:0];
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prgen_min3 #(8) min3(
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prgen_min3 #(8) min3(
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.clk(clk),
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.clk(clk),
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.reset(reset),
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.reset(reset),
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.a(max_burst_align), //address constraint
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.a(max_burst_align), //address constraint
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.b(burst_max_size), //sw constraint
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.b(burst_max_size), //sw constraint
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.c(x_remain_fifo), //buffer constraint
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.c(x_remain_fifo), //buffer constraint
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.min(burst_size_pre)
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.min(burst_size_pre)
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);
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);
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//
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//
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//address align, do not cross 16 bit or 32 bit boundary
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//address align, do not cross 16 bit or 32 bit boundary
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assign max_burst_align =
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assign max_burst_align =
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burst_addr[0] ? 'd1 : // byte
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burst_addr[0] ? 'd1 : // byte
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burst_addr[1] ? 'd2 : // 16 bit
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burst_addr[1] ? 'd2 : // 16 bit
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burst_addr[2] ? 'd4 : // 32 bit
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burst_addr[2] ? 'd4 : // 32 bit
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{1'b1, {8-1{1'b0}}}; //no restriction
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{1'b1, {8-1{1'b0}}}; //no restriction
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assign burst_size_pre2 =
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assign burst_size_pre2 =
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|burst_size_pre[8-1:3] ? {burst_size_pre[8-1:3], 3'b000} : //burst
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|burst_size_pre[8-1:3] ? {burst_size_pre[8-1:3], 3'b000} : //burst
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burst_size_pre[2] ? 'd4 :
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burst_size_pre[2] ? 'd4 :
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burst_size_pre[1] ? 'd2 :
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burst_size_pre[1] ? 'd2 :
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burst_size_pre[0] ? 'd1 : 'd0;
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burst_size_pre[0] ? 'd1 : 'd0;
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assign fifo_not_ready_pre = (fifo_remain < burst_size_pre2) & (~release_fifo);
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assign fifo_not_ready_pre = (fifo_remain < burst_size_pre2) & (~release_fifo);
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prgen_delay #(1) delay_fifo_not_ready (.clk(clk), .reset(reset), .din(fifo_not_ready_pre), .dout(fifo_not_ready));
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prgen_delay #(1) delay_fifo_not_ready (.clk(clk), .reset(reset), .din(fifo_not_ready_pre), .dout(fifo_not_ready));
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assign burst_last = burst_size == x_remain;
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assign burst_last = burst_size == x_remain;
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always @(posedge clk or posedge reset)
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always @(posedge clk or posedge reset)
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if (reset)
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if (reset)
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burst_ready <= #1 1'b0;
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burst_ready <= #1 1'b0;
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else if (ch_update | ch_update_d | ch_update_d2 | ch_update_d3)
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else if (ch_update | ch_update_d | ch_update_d2 | ch_update_d3)
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burst_ready <= #1 1'b0;
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burst_ready <= #1 1'b0;
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else if (load_req_in_prog)
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else if (load_req_in_prog)
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burst_ready <= #1 1'b1;
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burst_ready <= #1 1'b1;
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else if (|joint_burst_req)
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else if (|joint_burst_req)
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burst_ready <= #1 1'b1;
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burst_ready <= #1 1'b1;
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else if (joint_line_req & (~joint_buffer_small))
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else if (joint_line_req & (~joint_buffer_small))
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burst_ready <= #1 1'b1;
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burst_ready <= #1 1'b1;
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else if (load_in_prog | fifo_not_ready_pre | joint_wait | (page_cross & (burst_size != burst_size_pre2)))
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else if (load_in_prog | fifo_not_ready_pre | joint_wait | (page_cross & (burst_size != burst_size_pre2)))
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burst_ready <= #1 1'b0;
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burst_ready <= #1 1'b0;
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else
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else
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burst_ready <= #1 |burst_size_pre2;
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burst_ready <= #1 |burst_size_pre2;
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always @(posedge clk or posedge reset)
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always @(posedge clk or posedge reset)
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if (reset)
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if (reset)
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burst_size <= #1 {8{1'b0}};
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burst_size <= #1 {8{1'b0}};
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else if (load_req_in_prog)
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else if (load_req_in_prog)
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burst_size <= #1 CMD_SIZE;
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burst_size <= #1 CMD_SIZE;
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else if (|joint_burst_req)
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else if (|joint_burst_req)
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burst_size <= #1 joint_burst_req_size;
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burst_size <= #1 joint_burst_req_size;
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else if (joint_line_req & (~joint_buffer_small))
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else if (joint_line_req & (~joint_buffer_small))
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burst_size <= #1 joint_line_req_size;
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burst_size <= #1 joint_line_req_size;
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else
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else
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burst_size <= #1 burst_size_pre2;
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burst_size <= #1 burst_size_pre2;
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assign joint_update = ch_update | ch_update_d | ch_update_d2;
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assign joint_update = ch_update | ch_update_d | ch_update_d2;
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always @(posedge clk or posedge reset)
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always @(posedge clk or posedge reset)
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if (reset)
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if (reset)
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joint_burst_req_reg <= #1 2'b00;
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joint_burst_req_reg <= #1 2'b00;
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else if (joint_update | joint_flush | joint_flush_in)
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else if (joint_update | joint_flush | joint_flush_in)
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joint_burst_req_reg <= #1 2'b00;
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joint_burst_req_reg <= #1 2'b00;
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else if (joint_burst_req_reg & burst_start)
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else if (joint_burst_req_reg & burst_start)
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joint_burst_req_reg <= #1 2'b00;
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joint_burst_req_reg <= #1 2'b00;
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else if (joint_burst_req_in)
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else if (joint_burst_req_in)
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joint_burst_req_reg <= #1 joint_burst_req_reg[0] ? 2'b11 : 2'b01;
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joint_burst_req_reg <= #1 joint_burst_req_reg[0] ? 2'b11 : 2'b01;
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assign joint_burst_req = joint_burst_req_reg;
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assign joint_burst_req = joint_burst_req_reg;
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always @(posedge clk or posedge reset)
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always @(posedge clk or posedge reset)
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if (reset)
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if (reset)
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joint_line_req_reg <= #1 1'b0;
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joint_line_req_reg <= #1 1'b0;
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else if (joint_update | joint_flush | joint_flush_in)
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else if (joint_update | joint_flush | joint_flush_in)
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joint_line_req_reg <= #1 1'b0;
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joint_line_req_reg <= #1 1'b0;
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else if (joint_line_req_reg & burst_start)
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else if (joint_line_req_reg & burst_start)
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joint_line_req_reg <= #1 1'b0;
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joint_line_req_reg <= #1 1'b0;
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else if (joint_line_req_in)
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else if (joint_line_req_in)
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joint_line_req_reg <= #1 1'b1;
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joint_line_req_reg <= #1 1'b1;
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assign joint_line_req = joint_line_req_reg;
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assign joint_line_req = joint_line_req_reg;
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assign joint_line_req_size =
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assign joint_line_req_size =
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burst_addr[2:0] == 3'd0 ? 4'd8 :
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burst_addr[2:0] == 3'd0 ? 4'd8 :
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burst_addr[1:0] == 2'd0 ? 'd4 :
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burst_addr[1:0] == 2'd0 ? 'd4 :
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burst_addr[0] == 1'd0 ? 'd2 : 'd1;
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burst_addr[0] == 1'd0 ? 'd2 : 'd1;
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assign joint_burst_req_size =
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assign joint_burst_req_size =
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burst_addr[0] ? 'd1 :
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burst_addr[0] ? 'd1 :
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burst_addr[1] ? 'd2 :
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burst_addr[1] ? 'd2 :
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burst_addr[2] & (!0) ? 'd4 :
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burst_addr[2] & (!0) ? 'd4 :
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joint_burst_req[1] ? 'd32 : 'd16;
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joint_burst_req[1] ? 'd32 : 'd16;
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dma_axi64_core0_ch_calc_joint #(READ)
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dma_axi64_core0_ch_calc_joint #(READ)
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dma_axi64_core0_ch_calc_joint (
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dma_axi64_core0_ch_calc_joint (
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.clk(clk),
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.clk(clk),
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.reset(reset),
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.reset(reset),
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.joint_update(joint_update),
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.joint_update(joint_update),
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.ch_end(ch_end),
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.ch_end(ch_end),
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.ch_end_flush(ch_end_flush),
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.ch_end_flush(ch_end_flush),
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.joint_line_req_clr(joint_line_req_clr),
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.joint_line_req_clr(joint_line_req_clr),
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.burst_size_pre2(burst_size_pre2),
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.burst_size_pre2(burst_size_pre2),
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.burst_max_size(burst_max_size),
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.burst_max_size(burst_max_size),
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.fifo_not_ready(fifo_not_ready),
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.fifo_not_ready(fifo_not_ready),
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.wr_cmd_pending(wr_cmd_pending),
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.wr_cmd_pending(wr_cmd_pending),
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.outs_empty(outs_empty),
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.outs_empty(outs_empty),
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.x_remain(x_remain),
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.x_remain(x_remain),
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.fifo_wr_ready(fifo_wr_ready),
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.fifo_wr_ready(fifo_wr_ready),
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.fifo_remain(fifo_remain),
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.fifo_remain(fifo_remain),
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.joint(joint),
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.joint(joint),
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.joint_ready_in(joint_ready_in),
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.joint_ready_in(joint_ready_in),
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.joint_ready_out(joint_ready_out),
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.joint_ready_out(joint_ready_out),
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.joint_line_req(joint_line_req_out),
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.joint_line_req(joint_line_req_out),
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.joint_burst_req(joint_burst_req_out),
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.joint_burst_req(joint_burst_req_out),
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.joint_wait(joint_wait),
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.joint_wait(joint_wait),
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.page_cross(page_cross),
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.page_cross(page_cross),
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.joint_cross(joint_cross),
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.joint_cross(joint_cross),
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.joint_flush(joint_flush),
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.joint_flush(joint_flush),
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.joint_flush_in(joint_flush_in),
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.joint_flush_in(joint_flush_in),
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.joint_buffer_small(joint_buffer_small)
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.joint_buffer_small(joint_buffer_small)
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);
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);
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assign release_fifo = joint_ready_in & joint_ready_out & (~joint_cross);
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assign release_fifo = joint_ready_in & joint_ready_out & (~joint_cross);
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endmodule
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endmodule
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