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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Author: Eyal Hochberg ////
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//// eyal@provartec.com ////
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//// ////
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//// Downloaded from: http://www.opencores.org ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2010 Provartec LTD ////
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//// www.provartec.com ////
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//// info@provartec.com ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation.////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more////
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//// details. http://www.gnu.org/licenses/lgpl.html ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//---------------------------------------------------------
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//---------------------------------------------------------
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//-- File generated by RobustVerilog parser
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//-- File generated by RobustVerilog parser
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//-- Version: 1.0
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//-- Version: 1.0
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//-- Invoked Fri Mar 25 23:36:57 2011
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//-- Invoked Fri Mar 25 23:36:57 2011
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//--
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//--
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//-- Source file: dma_ch_fifo.v
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//-- Source file: dma_ch_fifo.v
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//---------------------------------------------------------
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//---------------------------------------------------------
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module dma_axi64_core0_ch_fifo (CLK,WR,RD,WR_ADDR,RD_ADDR,DIN,BSEL,DOUT);
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module dma_axi64_core0_ch_fifo (CLK,WR,RD,WR_ADDR,RD_ADDR,DIN,BSEL,DOUT);
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input CLK;
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input CLK;
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input WR;
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input WR;
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input RD;
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input RD;
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input [5-3-1:0] WR_ADDR;
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input [5-3-1:0] WR_ADDR;
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input [5-3-1:0] RD_ADDR;
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input [5-3-1:0] RD_ADDR;
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input [64-1:0] DIN;
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input [64-1:0] DIN;
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input [8-1:0] BSEL;
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input [8-1:0] BSEL;
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output [64-1:0] DOUT;
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output [64-1:0] DOUT;
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reg [64-1:0] Mem [4-1:0];
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reg [64-1:0] Mem [4-1:0];
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wire [64-1:0] BitSEL;
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wire [64-1:0] BitSEL;
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wire [64-1:0] DIN_BitSEL;
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wire [64-1:0] DIN_BitSEL;
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reg [64-1:0] DOUT;
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reg [64-1:0] DOUT;
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assign BitSEL = {{8{BSEL[7]}} , {8{BSEL[6]}} , {8{BSEL[5]}} , {8{BSEL[4]}} , {8{BSEL[3]}} , {8{BSEL[2]}} , {8{BSEL[1]}} , {8{BSEL[0]}}};
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assign BitSEL = {{8{BSEL[7]}} , {8{BSEL[6]}} , {8{BSEL[5]}} , {8{BSEL[4]}} , {8{BSEL[3]}} , {8{BSEL[2]}} , {8{BSEL[1]}} , {8{BSEL[0]}}};
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assign DIN_BitSEL = (Mem[WR_ADDR] & ~BitSEL) | (DIN & BitSEL);
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assign DIN_BitSEL = (Mem[WR_ADDR] & ~BitSEL) | (DIN & BitSEL);
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always @(posedge CLK)
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always @(posedge CLK)
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if (WR)
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if (WR)
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Mem[WR_ADDR] <= #1 DIN_BitSEL;
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Mem[WR_ADDR] <= #1 DIN_BitSEL;
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always @(posedge CLK)
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always @(posedge CLK)
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if (RD)
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if (RD)
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DOUT <= #1 Mem[RD_ADDR];
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DOUT <= #1 Mem[RD_ADDR];
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endmodule
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endmodule
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