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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Author: Eyal Hochberg ////
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//// eyal@provartec.com ////
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//// ////
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//// Downloaded from: http://www.opencores.org ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2010 Provartec LTD ////
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//// www.provartec.com ////
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//// info@provartec.com ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation.////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more////
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//// details. http://www.gnu.org/licenses/lgpl.html ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//---------------------------------------------------------
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//---------------------------------------------------------
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//-- File generated by RobustVerilog parser
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//-- File generated by RobustVerilog parser
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//-- Version: 1.0
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//-- Version: 1.0
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//-- Invoked Fri Mar 25 23:36:56 2011
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//-- Invoked Fri Mar 25 23:36:56 2011
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//--
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//--
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//-- Source file: dma_ch_reg.v
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//-- Source file: dma_ch_reg.v
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//---------------------------------------------------------
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//---------------------------------------------------------
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module dma_axi64_core0_ch_reg(clk,clken,pclken,reset,psel,penable,paddr,pwrite,pwdata,prdata,pslverr,timeout_bus,wdt_timeout,ch_start,load_addr,load_in_prog,load_req_in_prog,load_wr,load_wr_cycle,load_wdata,load_cmd,rd_ch_end,wr_ch_end,wr_clr_last,rd_slverr,rd_decerr,wr_slverr,wr_decerr,int_all_proc,ch_rd_active,ch_wr_active,ch_in_prog,rd_x_offset,rd_y_offset,wr_x_offset,wr_y_offset,wr_fullness,rd_gap,fifo_overflow,fifo_underflow,ch_update,rd_start_addr,wr_start_addr,x_size,y_size,rd_burst_max_size,wr_burst_max_size,block,allow_line_cmd,frame_width,width_align,rd_periph_delay,rd_periph_block,wr_periph_delay,wr_periph_block,rd_tokens,wr_tokens,rd_port_num,wr_port_num,rd_outs_max,wr_outs_max,rd_outs,wr_outs,outs_empty,rd_wait_limit,wr_wait_limit,rd_incr,wr_incr,rd_periph_num,wr_periph_num,wr_outstanding,rd_outstanding,ch_retry_wait,joint_mode,joint_remote,joint_cross,page_cross,joint,joint_flush,end_swap);
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module dma_axi64_core0_ch_reg(clk,clken,pclken,reset,psel,penable,paddr,pwrite,pwdata,prdata,pslverr,timeout_bus,wdt_timeout,ch_start,load_addr,load_in_prog,load_req_in_prog,load_wr,load_wr_cycle,load_wdata,load_cmd,rd_ch_end,wr_ch_end,wr_clr_last,rd_slverr,rd_decerr,wr_slverr,wr_decerr,int_all_proc,ch_rd_active,ch_wr_active,ch_in_prog,rd_x_offset,rd_y_offset,wr_x_offset,wr_y_offset,wr_fullness,rd_gap,fifo_overflow,fifo_underflow,ch_update,rd_start_addr,wr_start_addr,x_size,y_size,rd_burst_max_size,wr_burst_max_size,block,allow_line_cmd,frame_width,width_align,rd_periph_delay,rd_periph_block,wr_periph_delay,wr_periph_block,rd_tokens,wr_tokens,rd_port_num,wr_port_num,rd_outs_max,wr_outs_max,rd_outs,wr_outs,outs_empty,rd_wait_limit,wr_wait_limit,rd_incr,wr_incr,rd_periph_num,wr_periph_num,wr_outstanding,rd_outstanding,ch_retry_wait,joint_mode,joint_remote,joint_cross,page_cross,joint,joint_flush,end_swap);
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parameter DATA_SHIFT = 0 ? 32 : 0;
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parameter DATA_SHIFT = 0 ? 32 : 0;
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input clk;
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input clk;
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input clken;
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input clken;
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input pclken;
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input pclken;
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input reset;
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input reset;
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input psel;
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input psel;
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input penable;
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input penable;
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input [7:0] paddr;
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input [7:0] paddr;
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input pwrite;
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input pwrite;
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input [31:0] pwdata;
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input [31:0] pwdata;
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output [31:0] prdata;
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output [31:0] prdata;
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output pslverr;
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output pslverr;
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input [4:0] timeout_bus;
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input [4:0] timeout_bus;
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input wdt_timeout;
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input wdt_timeout;
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input ch_start;
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input ch_start;
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output [32-1:0] load_addr;
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output [32-1:0] load_addr;
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output load_in_prog;
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output load_in_prog;
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output load_req_in_prog;
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output load_req_in_prog;
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input load_wr;
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input load_wr;
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input [1:0] load_wr_cycle;
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input [1:0] load_wr_cycle;
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input [64-1:0] load_wdata;
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input [64-1:0] load_wdata;
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input load_cmd;
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input load_cmd;
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input rd_ch_end;
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input rd_ch_end;
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input wr_ch_end;
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input wr_ch_end;
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input wr_clr_last;
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input wr_clr_last;
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input rd_slverr;
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input rd_slverr;
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input rd_decerr;
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input rd_decerr;
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input wr_slverr;
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input wr_slverr;
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input wr_decerr;
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input wr_decerr;
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output [1-1:0] int_all_proc;
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output [1-1:0] int_all_proc;
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output ch_rd_active;
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output ch_rd_active;
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output ch_wr_active;
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output ch_wr_active;
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output ch_in_prog;
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output ch_in_prog;
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input [10-1:0] rd_x_offset;
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input [10-1:0] rd_x_offset;
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input [10-`X_BITS-1:0] rd_y_offset;
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input [10-`X_BITS-1:0] rd_y_offset;
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input [10-1:0] wr_x_offset;
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input [10-1:0] wr_x_offset;
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input [10-`X_BITS-1:0] wr_y_offset;
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input [10-`X_BITS-1:0] wr_y_offset;
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input [5:0] wr_fullness;
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input [5:0] wr_fullness;
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input [5:0] rd_gap;
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input [5:0] rd_gap;
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input fifo_overflow;
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input fifo_overflow;
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input fifo_underflow;
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input fifo_underflow;
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output ch_update;
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output ch_update;
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output [32-1:0] rd_start_addr;
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output [32-1:0] rd_start_addr;
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output [32-1:0] wr_start_addr;
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output [32-1:0] wr_start_addr;
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output [10-1:0] x_size;
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output [10-1:0] x_size;
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output [10-`X_BITS-1:0] y_size;
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output [10-`X_BITS-1:0] y_size;
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output [8-1:0] rd_burst_max_size;
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output [8-1:0] rd_burst_max_size;
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output [8-1:0] wr_burst_max_size;
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output [8-1:0] wr_burst_max_size;
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output block;
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output block;
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input allow_line_cmd;
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input allow_line_cmd;
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output [`FRAME_BITS-1:0] frame_width;
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output [`FRAME_BITS-1:0] frame_width;
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output [3-1:0] width_align;
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output [3-1:0] width_align;
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output [`DELAY_BITS-1:0] rd_periph_delay;
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output [`DELAY_BITS-1:0] rd_periph_delay;
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output rd_periph_block;
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output rd_periph_block;
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output [`DELAY_BITS-1:0] wr_periph_delay;
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output [`DELAY_BITS-1:0] wr_periph_delay;
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output wr_periph_block;
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output wr_periph_block;
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output [`TOKEN_BITS-1:0] rd_tokens;
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output [`TOKEN_BITS-1:0] rd_tokens;
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output [`TOKEN_BITS-1:0] wr_tokens;
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output [`TOKEN_BITS-1:0] wr_tokens;
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output rd_port_num;
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output rd_port_num;
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output wr_port_num;
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output wr_port_num;
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output [`OUT_BITS-1:0] rd_outs_max;
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output [`OUT_BITS-1:0] rd_outs_max;
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output [`OUT_BITS-1:0] wr_outs_max;
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output [`OUT_BITS-1:0] wr_outs_max;
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input [`OUT_BITS-1:0] rd_outs;
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input [`OUT_BITS-1:0] rd_outs;
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input [`OUT_BITS-1:0] wr_outs;
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input [`OUT_BITS-1:0] wr_outs;
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input outs_empty;
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input outs_empty;
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output [`WAIT_BITS-1:0] rd_wait_limit;
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output [`WAIT_BITS-1:0] rd_wait_limit;
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output [`WAIT_BITS-1:0] wr_wait_limit;
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output [`WAIT_BITS-1:0] wr_wait_limit;
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output rd_incr;
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output rd_incr;
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output wr_incr;
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output wr_incr;
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output [4:0] rd_periph_num;
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output [4:0] rd_periph_num;
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output [4:0] wr_periph_num;
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output [4:0] wr_periph_num;
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output wr_outstanding;
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output wr_outstanding;
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output rd_outstanding;
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output rd_outstanding;
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output ch_retry_wait;
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output ch_retry_wait;
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input joint_mode;
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input joint_mode;
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input joint_remote;
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input joint_remote;
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input joint_cross;
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input joint_cross;
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input page_cross;
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input page_cross;
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output joint;
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output joint;
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input joint_flush;
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input joint_flush;
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output [1:0] end_swap;
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output [1:0] end_swap;
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`include "dma_axi64_ch_reg_params.v"
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`include "dma_axi64_ch_reg_params.v"
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parameter INT_NUM = 13;
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parameter INT_NUM = 13;
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wire [7:0] gpaddr;
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wire [7:0] gpaddr;
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wire gpwrite;
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wire gpwrite;
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wire gpread;
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wire gpread;
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reg [31:0] prdata_pre;
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reg [31:0] prdata_pre;
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reg pslverr_pre;
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reg pslverr_pre;
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reg [31:0] prdata;
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reg [31:0] prdata;
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reg pslverr;
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reg pslverr;
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reg ch_enable;
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reg ch_enable;
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reg ch_in_prog;
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reg ch_in_prog;
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reg rd_ch_in_prog;
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reg rd_ch_in_prog;
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reg wr_ch_in_prog;
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reg wr_ch_in_prog;
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reg load_in_prog_reg;
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reg load_in_prog_reg;
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reg load_req_in_prog_reg;
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reg load_req_in_prog_reg;
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//current cmd
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//current cmd
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reg [32-1:0] rd_start_addr;
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reg [32-1:0] rd_start_addr;
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reg [32-1:0] wr_start_addr;
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reg [32-1:0] wr_start_addr;
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reg [10-1:0] buff_size;
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reg [10-1:0] buff_size;
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wire [10-1:0] x_size;
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wire [10-1:0] x_size;
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wire [10-`X_BITS-1:0] y_size;
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wire [10-`X_BITS-1:0] y_size;
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reg [`FRAME_BITS-1:0] frame_width_reg;
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reg [`FRAME_BITS-1:0] frame_width_reg;
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reg block_reg;
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reg block_reg;
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reg joint_reg;
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reg joint_reg;
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reg simple_mem;
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reg simple_mem;
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wire joint;
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wire joint;
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wire joint_mux;
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wire joint_mux;
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reg auto_retry_reg;
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reg auto_retry_reg;
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wire auto_retry;
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wire auto_retry;
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reg [1:0] end_swap_reg;
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reg [1:0] end_swap_reg;
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//static
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//static
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wire [8-1:0] rd_burst_max_size_rd;
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wire [8-1:0] rd_burst_max_size_rd;
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wire [8-1:0] rd_burst_max_size_pre;
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wire [8-1:0] rd_burst_max_size_pre;
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reg [8-1:0] rd_burst_max_size_reg;
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reg [8-1:0] rd_burst_max_size_reg;
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reg [`DELAY_BITS-1:0] rd_periph_delay_reg;
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reg [`DELAY_BITS-1:0] rd_periph_delay_reg;
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reg rd_periph_block_reg;
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reg rd_periph_block_reg;
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reg [`TOKEN_BITS-1:0] rd_tokens_reg;
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reg [`TOKEN_BITS-1:0] rd_tokens_reg;
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reg [`OUT_BITS-1:0] rd_outs_max_reg;
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reg [`OUT_BITS-1:0] rd_outs_max_reg;
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reg rd_port_num_reg;
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reg rd_port_num_reg;
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reg cmd_port_num_reg;
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reg cmd_port_num_reg;
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wire rd_port_num_cfg;
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wire rd_port_num_cfg;
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wire cmd_port_num;
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wire cmd_port_num;
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reg rd_outstanding_reg;
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reg rd_outstanding_reg;
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wire rd_outstanding_cfg;
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wire rd_outstanding_cfg;
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reg rd_incr_reg;
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reg rd_incr_reg;
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reg [4:0] rd_periph_num_reg;
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reg [4:0] rd_periph_num_reg;
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reg [`WAIT_BITS-1:4] rd_wait_limit_reg;
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reg [`WAIT_BITS-1:4] rd_wait_limit_reg;
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wire [8-1:0] wr_burst_max_size_rd;
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wire [8-1:0] wr_burst_max_size_rd;
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wire [8-1:0] wr_burst_max_size_pre;
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wire [8-1:0] wr_burst_max_size_pre;
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reg [8-1:0] wr_burst_max_size_reg;
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reg [8-1:0] wr_burst_max_size_reg;
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reg [`DELAY_BITS-1:0] wr_periph_delay_reg;
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reg [`DELAY_BITS-1:0] wr_periph_delay_reg;
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reg wr_periph_block_reg;
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reg wr_periph_block_reg;
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reg [`TOKEN_BITS-1:0] wr_tokens_reg;
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reg [`TOKEN_BITS-1:0] wr_tokens_reg;
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reg [`OUT_BITS-1:0] wr_outs_max_reg;
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reg [`OUT_BITS-1:0] wr_outs_max_reg;
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reg wr_port_num_reg;
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reg wr_port_num_reg;
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reg wr_outstanding_reg;
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reg wr_outstanding_reg;
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wire wr_outstanding_cfg;
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wire wr_outstanding_cfg;
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reg wr_incr_reg;
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reg wr_incr_reg;
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reg [4:0] wr_periph_num_reg;
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reg [4:0] wr_periph_num_reg;
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reg [`WAIT_BITS-1:4] wr_wait_limit_reg;
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reg [`WAIT_BITS-1:4] wr_wait_limit_reg;
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wire rd_allow_full_fifo;
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wire rd_allow_full_fifo;
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wire wr_allow_full_fifo;
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wire wr_allow_full_fifo;
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wire allow_full_fifo;
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wire allow_full_fifo;
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wire allow_full_burst;
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wire allow_full_burst;
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wire allow_joint_burst;
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wire allow_joint_burst;
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wire burst_max_size_update_pre;
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wire burst_max_size_update_pre;
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wire burst_max_size_update;
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wire burst_max_size_update;
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reg cmd_set_int_reg;
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reg cmd_set_int_reg;
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reg cmd_last_reg;
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reg cmd_last_reg;
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reg [32-1:2] cmd_next_addr_reg;
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reg [32-1:2] cmd_next_addr_reg;
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reg [`CMD_CNT_BITS-1:0] cmd_counter_reg;
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reg [`CMD_CNT_BITS-1:0] cmd_counter_reg;
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reg [`INT_CNT_BITS-1:0] int_counter_reg;
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reg [`INT_CNT_BITS-1:0] int_counter_reg;
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wire cmd_set_int;
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wire cmd_set_int;
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wire cmd_last;
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wire cmd_last;
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wire [32-1:2] cmd_next_addr;
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wire [32-1:2] cmd_next_addr;
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wire [`CMD_CNT_BITS-1:0] cmd_counter;
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wire [`CMD_CNT_BITS-1:0] cmd_counter;
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wire [`INT_CNT_BITS-1:0] int_counter;
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wire [`INT_CNT_BITS-1:0] int_counter;
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//interrupt
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//interrupt
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wire ch_end;
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wire ch_end;
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wire ch_end_set;
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wire ch_end_set;
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wire ch_end_clear;
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wire ch_end_clear;
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wire ch_end_int;
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wire ch_end_int;
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wire [2:0] int_proc_num;
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wire [2:0] int_proc_num;
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reg [2:0] int_proc_num_reg;
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reg [2:0] int_proc_num_reg;
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wire [INT_NUM-1:0] int_bus;
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wire [INT_NUM-1:0] int_bus;
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wire [INT_NUM-1:0] int_rawstat;
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wire [INT_NUM-1:0] int_rawstat;
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reg [INT_NUM-1:0] int_enable;
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reg [INT_NUM-1:0] int_enable;
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wire [INT_NUM-1:0] int_status;
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wire [INT_NUM-1:0] int_status;
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wire [7:0] int_all_proc_bus;
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wire [7:0] int_all_proc_bus;
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wire wr_cmd_line0;
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wire wr_cmd_line0;
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wire wr_cmd_line1;
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wire wr_cmd_line1;
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wire wr_cmd_line2;
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wire wr_cmd_line2;
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wire wr_cmd_line3;
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wire wr_cmd_line3;
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wire wr_static_line0;
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wire wr_static_line0;
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wire wr_static_line1;
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wire wr_static_line1;
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wire wr_static_line2;
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wire wr_static_line2;
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wire wr_static_line3;
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wire wr_static_line3;
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wire wr_static_line4;
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wire wr_static_line4;
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wire wr_ch_enable;
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wire wr_ch_enable;
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wire wr_ch_start;
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wire wr_ch_start;
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wire wr_int_rawstat;
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wire wr_int_rawstat;
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wire wr_int_clear;
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wire wr_int_clear;
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wire wr_int_enable;
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wire wr_int_enable;
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wire wr_frame_width;
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wire wr_frame_width;
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reg [31:0] rd_cmd_line0;
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reg [31:0] rd_cmd_line0;
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reg [31:0] rd_cmd_line1;
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reg [31:0] rd_cmd_line1;
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reg [31:0] rd_cmd_line2;
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reg [31:0] rd_cmd_line2;
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reg [31:0] rd_cmd_line3;
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reg [31:0] rd_cmd_line3;
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reg [31:0] rd_static_line0;
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reg [31:0] rd_static_line0;
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reg [31:0] rd_static_line1;
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reg [31:0] rd_static_line1;
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reg [31:0] rd_static_line2;
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reg [31:0] rd_static_line2;
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reg [31:0] rd_static_line3;
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reg [31:0] rd_static_line3;
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reg [31:0] rd_static_line4;
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reg [31:0] rd_static_line4;
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reg [31:0] rd_restrict;
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reg [31:0] rd_restrict;
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reg [31:0] rd_rd_offsets;
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reg [31:0] rd_rd_offsets;
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reg [31:0] rd_wr_offsets;
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reg [31:0] rd_wr_offsets;
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reg [31:0] rd_fifo_fullness;
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reg [31:0] rd_fifo_fullness;
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reg [31:0] rd_cmd_outs;
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reg [31:0] rd_cmd_outs;
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reg [31:0] rd_ch_enable;
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reg [31:0] rd_ch_enable;
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reg [31:0] rd_ch_active;
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reg [31:0] rd_ch_active;
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reg [31:0] rd_cmd_counter;
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reg [31:0] rd_cmd_counter;
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reg [31:0] rd_int_rawstat;
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reg [31:0] rd_int_rawstat;
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reg [31:0] rd_int_enable;
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reg [31:0] rd_int_enable;
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reg [31:0] rd_int_status;
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reg [31:0] rd_int_status;
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wire load_wr_cycle0;
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wire load_wr_cycle0;
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wire load_wr_cycle1;
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wire load_wr_cycle1;
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wire load_wr_cycle2;
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wire load_wr_cycle2;
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wire load_wr_cycle3;
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wire load_wr_cycle3;
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wire load_wr0;
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wire load_wr0;
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wire load_wr1;
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wire load_wr1;
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wire load_wr2;
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wire load_wr2;
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wire load_wr3;
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wire load_wr3;
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wire load_wr_last;
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wire load_wr_last;
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wire load_req;
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wire load_req;
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|
wire timeout_aw;
|
wire timeout_aw;
|
wire timeout_w;
|
wire timeout_w;
|
wire timeout_b;
|
wire timeout_b;
|
wire timeout_ar;
|
wire timeout_ar;
|
wire timeout_r;
|
wire timeout_r;
|
|
|
wire ch_retry_wait_pre;
|
wire ch_retry_wait_pre;
|
reg ch_retry_wait_reg;
|
reg ch_retry_wait_reg;
|
wire ch_retry_wait;
|
wire ch_retry_wait;
|
wire ch_retry;
|
wire ch_retry;
|
wire ch_update_pre;
|
wire ch_update_pre;
|
reg ch_update;
|
reg ch_update;
|
wire ch_update_d;
|
wire ch_update_d;
|
|
|
wire ch_int;
|
wire ch_int;
|
|
|
|
|
//---------------------- gating -------------------------------------
|
//---------------------- gating -------------------------------------
|
|
|
|
|
//assign gpaddr = {8{psel}} & paddr;
|
//assign gpaddr = {8{psel}} & paddr;
|
assign gpaddr = paddr; //removed for timing
|
assign gpaddr = paddr; //removed for timing
|
assign gpwrite = psel & (~penable) & pwrite;
|
assign gpwrite = psel & (~penable) & pwrite;
|
assign gpread = psel & (~penable) & (~pwrite);
|
assign gpread = psel & (~penable) & (~pwrite);
|
|
|
|
|
//---------------------- Write Operations ----------------------------------
|
//---------------------- Write Operations ----------------------------------
|
assign wr_cmd_line0 = gpwrite & gpaddr == CMD_LINE0;
|
assign wr_cmd_line0 = gpwrite & gpaddr == CMD_LINE0;
|
assign wr_cmd_line1 = gpwrite & gpaddr == CMD_LINE1;
|
assign wr_cmd_line1 = gpwrite & gpaddr == CMD_LINE1;
|
assign wr_cmd_line2 = gpwrite & gpaddr == CMD_LINE2;
|
assign wr_cmd_line2 = gpwrite & gpaddr == CMD_LINE2;
|
assign wr_cmd_line3 = gpwrite & gpaddr == CMD_LINE3;
|
assign wr_cmd_line3 = gpwrite & gpaddr == CMD_LINE3;
|
assign wr_static_line0 = gpwrite & gpaddr == STATIC_LINE0;
|
assign wr_static_line0 = gpwrite & gpaddr == STATIC_LINE0;
|
assign wr_static_line1 = gpwrite & gpaddr == STATIC_LINE1;
|
assign wr_static_line1 = gpwrite & gpaddr == STATIC_LINE1;
|
assign wr_static_line2 = gpwrite & gpaddr == STATIC_LINE2;
|
assign wr_static_line2 = gpwrite & gpaddr == STATIC_LINE2;
|
assign wr_static_line3 = gpwrite & gpaddr == STATIC_LINE3;
|
assign wr_static_line3 = gpwrite & gpaddr == STATIC_LINE3;
|
assign wr_static_line4 = gpwrite & gpaddr == STATIC_LINE4;
|
assign wr_static_line4 = gpwrite & gpaddr == STATIC_LINE4;
|
assign wr_ch_enable = gpwrite & gpaddr == CH_ENABLE;
|
assign wr_ch_enable = gpwrite & gpaddr == CH_ENABLE;
|
assign wr_ch_start = (gpwrite & gpaddr == CH_START) | ch_start;
|
assign wr_ch_start = (gpwrite & gpaddr == CH_START) | ch_start;
|
assign wr_int_rawstat = gpwrite & gpaddr == INT_RAWSTAT;
|
assign wr_int_rawstat = gpwrite & gpaddr == INT_RAWSTAT;
|
assign wr_int_clear = gpwrite & gpaddr == INT_CLEAR;
|
assign wr_int_clear = gpwrite & gpaddr == INT_CLEAR;
|
assign wr_int_enable = gpwrite & gpaddr == INT_ENABLE;
|
assign wr_int_enable = gpwrite & gpaddr == INT_ENABLE;
|
|
|
assign load_wr_cycle0 = load_wr & load_wr_cycle == 2'd0;
|
assign load_wr_cycle0 = load_wr & load_wr_cycle == 2'd0;
|
assign load_wr_cycle1 = load_wr & load_wr_cycle == 2'd1;
|
assign load_wr_cycle1 = load_wr & load_wr_cycle == 2'd1;
|
assign load_wr_cycle2 = load_wr & load_wr_cycle == 2'd2;
|
assign load_wr_cycle2 = load_wr & load_wr_cycle == 2'd2;
|
assign load_wr_cycle3 = load_wr & load_wr_cycle == 2'd3;
|
assign load_wr_cycle3 = load_wr & load_wr_cycle == 2'd3;
|
|
|
assign load_wr0 = 0 ? load_wr_cycle0 : load_wr_cycle0;
|
assign load_wr0 = 0 ? load_wr_cycle0 : load_wr_cycle0;
|
assign load_wr1 = 0 ? load_wr_cycle1 : load_wr_cycle0;
|
assign load_wr1 = 0 ? load_wr_cycle1 : load_wr_cycle0;
|
assign load_wr2 = 0 ? load_wr_cycle2 : load_wr_cycle1;
|
assign load_wr2 = 0 ? load_wr_cycle2 : load_wr_cycle1;
|
assign load_wr3 = 0 ? load_wr_cycle3 : load_wr_cycle1;
|
assign load_wr3 = 0 ? load_wr_cycle3 : load_wr_cycle1;
|
|
|
assign load_wr_last = load_wr3;
|
assign load_wr_last = load_wr3;
|
|
|
|
|
|
|
|
|
always @(posedge clk or posedge reset)
|
always @(posedge clk or posedge reset)
|
if (reset)
|
if (reset)
|
begin
|
begin
|
rd_start_addr <= #1 {32{1'b0}};
|
rd_start_addr <= #1 {32{1'b0}};
|
end
|
end
|
else if (wr_cmd_line0)
|
else if (wr_cmd_line0)
|
begin
|
begin
|
rd_start_addr <= #1 pwdata[32-1:0];
|
rd_start_addr <= #1 pwdata[32-1:0];
|
end
|
end
|
else if (load_wr0)
|
else if (load_wr0)
|
begin
|
begin
|
rd_start_addr <= #1 load_wdata[32-1:0];
|
rd_start_addr <= #1 load_wdata[32-1:0];
|
end
|
end
|
|
|
always @(posedge clk or posedge reset)
|
always @(posedge clk or posedge reset)
|
if (reset)
|
if (reset)
|
begin
|
begin
|
wr_start_addr <= #1 {32{1'b0}};
|
wr_start_addr <= #1 {32{1'b0}};
|
end
|
end
|
else if (wr_cmd_line1)
|
else if (wr_cmd_line1)
|
begin
|
begin
|
wr_start_addr <= #1 pwdata[32-1:0];
|
wr_start_addr <= #1 pwdata[32-1:0];
|
end
|
end
|
else if (load_wr1)
|
else if (load_wr1)
|
begin
|
begin
|
wr_start_addr <= #1 load_wdata[32+32-DATA_SHIFT-1:32-DATA_SHIFT];
|
wr_start_addr <= #1 load_wdata[32+32-DATA_SHIFT-1:32-DATA_SHIFT];
|
end
|
end
|
|
|
always @(posedge clk or posedge reset)
|
always @(posedge clk or posedge reset)
|
if (reset)
|
if (reset)
|
begin
|
begin
|
buff_size <= #1 {10{1'b0}};
|
buff_size <= #1 {10{1'b0}};
|
end
|
end
|
else if (wr_cmd_line2)
|
else if (wr_cmd_line2)
|
begin
|
begin
|
buff_size <= #1 pwdata[10-1:0];
|
buff_size <= #1 pwdata[10-1:0];
|
end
|
end
|
else if (load_wr2)
|
else if (load_wr2)
|
begin
|
begin
|
buff_size <= #1 load_wdata[10-1:0];
|
buff_size <= #1 load_wdata[10-1:0];
|
end
|
end
|
|
|
always @(posedge clk or posedge reset)
|
always @(posedge clk or posedge reset)
|
if (reset)
|
if (reset)
|
begin
|
begin
|
cmd_set_int_reg <= #1 1'b0;
|
cmd_set_int_reg <= #1 1'b0;
|
cmd_last_reg <= #1 1'b0;
|
cmd_last_reg <= #1 1'b0;
|
cmd_next_addr_reg <= #1 {30{1'b0}};
|
cmd_next_addr_reg <= #1 {30{1'b0}};
|
end
|
end
|
else if (wr_cmd_line3)
|
else if (wr_cmd_line3)
|
begin
|
begin
|
cmd_set_int_reg <= #1 pwdata[0];
|
cmd_set_int_reg <= #1 pwdata[0];
|
cmd_last_reg <= #1 pwdata[1];
|
cmd_last_reg <= #1 pwdata[1];
|
cmd_next_addr_reg <= #1 pwdata[32-1:2];
|
cmd_next_addr_reg <= #1 pwdata[32-1:2];
|
end
|
end
|
else if (load_wr3)
|
else if (load_wr3)
|
begin
|
begin
|
cmd_set_int_reg <= #1 load_wdata[32-DATA_SHIFT];
|
cmd_set_int_reg <= #1 load_wdata[32-DATA_SHIFT];
|
cmd_last_reg <= #1 load_wdata[33-DATA_SHIFT];
|
cmd_last_reg <= #1 load_wdata[33-DATA_SHIFT];
|
cmd_next_addr_reg <= #1 load_wdata[32+32-DATA_SHIFT-1:34-DATA_SHIFT];
|
cmd_next_addr_reg <= #1 load_wdata[32+32-DATA_SHIFT-1:34-DATA_SHIFT];
|
end
|
end
|
|
|
always @(posedge clk or posedge reset)
|
always @(posedge clk or posedge reset)
|
if (reset)
|
if (reset)
|
cmd_counter_reg <= #1 {`CMD_CNT_BITS{1'b0}};
|
cmd_counter_reg <= #1 {`CMD_CNT_BITS{1'b0}};
|
else if (wr_ch_start)
|
else if (wr_ch_start)
|
cmd_counter_reg <= #1 {`CMD_CNT_BITS{1'b0}};
|
cmd_counter_reg <= #1 {`CMD_CNT_BITS{1'b0}};
|
else if (ch_end & clken)
|
else if (ch_end & clken)
|
cmd_counter_reg <= #1 cmd_counter_reg + 1'b1;
|
cmd_counter_reg <= #1 cmd_counter_reg + 1'b1;
|
|
|
|
|
always @(posedge clk or posedge reset)
|
always @(posedge clk or posedge reset)
|
if (reset)
|
if (reset)
|
int_counter_reg <= #1 {`INT_CNT_BITS{1'b0}};
|
int_counter_reg <= #1 {`INT_CNT_BITS{1'b0}};
|
else if (wr_ch_start)
|
else if (wr_ch_start)
|
int_counter_reg <= #1 {`INT_CNT_BITS{1'b0}};
|
int_counter_reg <= #1 {`INT_CNT_BITS{1'b0}};
|
else if ((ch_end_int & clken) | ch_end_clear)
|
else if ((ch_end_int & clken) | ch_end_clear)
|
int_counter_reg <= #1 int_counter_reg + (ch_end_int & clken) - ch_end_clear;
|
int_counter_reg <= #1 int_counter_reg + (ch_end_int & clken) - ch_end_clear;
|
|
|
assign cmd_set_int = cmd_set_int_reg;
|
assign cmd_set_int = cmd_set_int_reg;
|
assign cmd_last = cmd_last_reg;
|
assign cmd_last = cmd_last_reg;
|
assign cmd_next_addr = cmd_next_addr_reg;
|
assign cmd_next_addr = cmd_next_addr_reg;
|
|
|
assign cmd_counter = cmd_counter_reg;
|
assign cmd_counter = cmd_counter_reg;
|
assign int_counter = int_counter_reg;
|
assign int_counter = int_counter_reg;
|
|
|
|
|
assign x_size = block ? {{10-`X_BITS{1'b0}}, buff_size[`X_BITS-1:0]} : buff_size;
|
assign x_size = block ? {{10-`X_BITS{1'b0}}, buff_size[`X_BITS-1:0]} : buff_size;
|
assign y_size = block ? buff_size[10-1:`X_BITS] : 'd1;
|
assign y_size = block ? buff_size[10-1:`X_BITS] : 'd1;
|
|
|
|
|
always @(posedge clk or posedge reset)
|
always @(posedge clk or posedge reset)
|
if (reset)
|
if (reset)
|
begin
|
begin
|
rd_burst_max_size_reg <= #1 'd0;
|
rd_burst_max_size_reg <= #1 'd0;
|
rd_tokens_reg <= #1 'd1;
|
rd_tokens_reg <= #1 'd1;
|
rd_outs_max_reg <= #1 {`OUT_BITS{1'b0}};
|
rd_outs_max_reg <= #1 {`OUT_BITS{1'b0}};
|
rd_incr_reg <= #1 'd1;
|
rd_incr_reg <= #1 'd1;
|
end
|
end
|
else if (wr_static_line0)
|
else if (wr_static_line0)
|
begin
|
begin
|
rd_burst_max_size_reg <= #1 pwdata[8-1:0];
|
rd_burst_max_size_reg <= #1 pwdata[8-1:0];
|
rd_tokens_reg <= #1 pwdata[`TOKEN_BITS+16-1:16];
|
rd_tokens_reg <= #1 pwdata[`TOKEN_BITS+16-1:16];
|
rd_outs_max_reg <= #1 pwdata[`OUT_BITS+24-1:24];
|
rd_outs_max_reg <= #1 pwdata[`OUT_BITS+24-1:24];
|
rd_incr_reg <= #1 pwdata[31];
|
rd_incr_reg <= #1 pwdata[31];
|
end
|
end
|
|
|
|
|
always @(posedge clk or posedge reset)
|
always @(posedge clk or posedge reset)
|
if (reset)
|
if (reset)
|
begin
|
begin
|
wr_burst_max_size_reg <= #1 'd0;
|
wr_burst_max_size_reg <= #1 'd0;
|
wr_tokens_reg <= #1 'd1;
|
wr_tokens_reg <= #1 'd1;
|
wr_outs_max_reg <= #1 {`OUT_BITS{1'b0}};
|
wr_outs_max_reg <= #1 {`OUT_BITS{1'b0}};
|
wr_incr_reg <= #1 'd1;
|
wr_incr_reg <= #1 'd1;
|
end
|
end
|
else if (wr_static_line1)
|
else if (wr_static_line1)
|
begin
|
begin
|
wr_burst_max_size_reg <= #1 pwdata[8-1:0];
|
wr_burst_max_size_reg <= #1 pwdata[8-1:0];
|
wr_tokens_reg <= #1 pwdata[`TOKEN_BITS+16-1:16];
|
wr_tokens_reg <= #1 pwdata[`TOKEN_BITS+16-1:16];
|
wr_outs_max_reg <= #1 pwdata[`OUT_BITS+24-1:24];
|
wr_outs_max_reg <= #1 pwdata[`OUT_BITS+24-1:24];
|
wr_incr_reg <= #1 pwdata[31];
|
wr_incr_reg <= #1 pwdata[31];
|
end
|
end
|
|
|
assign rd_incr = rd_incr_reg;
|
assign rd_incr = rd_incr_reg;
|
assign wr_incr = wr_incr_reg;
|
assign wr_incr = wr_incr_reg;
|
|
|
assign rd_outstanding_cfg = 1'b0;
|
assign rd_outstanding_cfg = 1'b0;
|
assign wr_outstanding_cfg = 1'b0;
|
assign wr_outstanding_cfg = 1'b0;
|
assign rd_outstanding = 1'b0;
|
assign rd_outstanding = 1'b0;
|
assign wr_outstanding = 1'b0;
|
assign wr_outstanding = 1'b0;
|
|
|
assign rd_tokens = rd_tokens_reg;
|
assign rd_tokens = rd_tokens_reg;
|
assign wr_tokens = joint_mux ? rd_tokens_reg : wr_tokens_reg;
|
assign wr_tokens = joint_mux ? rd_tokens_reg : wr_tokens_reg;
|
|
|
assign rd_outs_max = rd_outs_max_reg;
|
assign rd_outs_max = rd_outs_max_reg;
|
assign wr_outs_max = joint_mux ? rd_outs_max_reg : wr_outs_max_reg;
|
assign wr_outs_max = joint_mux ? rd_outs_max_reg : wr_outs_max_reg;
|
|
|
|
|
assign rd_allow_full_fifo = rd_start_addr[5-1:0] == 'd0;
|
assign rd_allow_full_fifo = rd_start_addr[5-1:0] == 'd0;
|
assign wr_allow_full_fifo = wr_start_addr[5-1:0] == 'd0;
|
assign wr_allow_full_fifo = wr_start_addr[5-1:0] == 'd0;
|
|
|
assign allow_full_fifo = rd_allow_full_fifo & wr_allow_full_fifo;
|
assign allow_full_fifo = rd_allow_full_fifo & wr_allow_full_fifo;
|
|
|
assign rd_burst_max_size = rd_burst_max_size_pre;
|
assign rd_burst_max_size = rd_burst_max_size_pre;
|
assign wr_burst_max_size = joint_mux ? rd_burst_max_size_pre : wr_burst_max_size_pre;
|
assign wr_burst_max_size = joint_mux ? rd_burst_max_size_pre : wr_burst_max_size_pre;
|
|
|
assign allow_joint_burst = joint & (~joint_flush) & (~page_cross) & (~joint_cross);
|
assign allow_joint_burst = joint & (~joint_flush) & (~page_cross) & (~joint_cross);
|
|
|
assign allow_full_burst = allow_joint_burst;
|
assign allow_full_burst = allow_joint_burst;
|
|
|
assign burst_max_size_update_pre = ch_update | ch_update_d | joint;
|
assign burst_max_size_update_pre = ch_update | ch_update_d | joint;
|
|
|
prgen_delay #(1) delay_max_size_update (.clk(clk), .reset(reset), .din(burst_max_size_update_pre), .dout(burst_max_size_update));
|
prgen_delay #(1) delay_max_size_update (.clk(clk), .reset(reset), .din(burst_max_size_update_pre), .dout(burst_max_size_update));
|
|
|
dma_axi64_core0_ch_reg_size
|
dma_axi64_core0_ch_reg_size
|
dma_axi64_core0_ch_reg_size_rd (
|
dma_axi64_core0_ch_reg_size_rd (
|
.clk(clk),
|
.clk(clk),
|
.reset(reset),
|
.reset(reset),
|
.update(burst_max_size_update),
|
.update(burst_max_size_update),
|
.start_addr(rd_start_addr),
|
.start_addr(rd_start_addr),
|
.burst_max_size_reg(rd_burst_max_size_reg),
|
.burst_max_size_reg(rd_burst_max_size_reg),
|
.burst_max_size_other(wr_burst_max_size_rd),
|
.burst_max_size_other(wr_burst_max_size_rd),
|
.allow_full_burst(allow_full_burst),
|
.allow_full_burst(allow_full_burst),
|
.allow_full_fifo(allow_full_fifo),
|
.allow_full_fifo(allow_full_fifo),
|
.joint_flush(joint_flush),
|
.joint_flush(joint_flush),
|
.burst_max_size(rd_burst_max_size_pre)
|
.burst_max_size(rd_burst_max_size_pre)
|
);
|
);
|
|
|
|
|
dma_axi64_core0_ch_reg_size
|
dma_axi64_core0_ch_reg_size
|
dma_axi64_core0_ch_reg_size_wr (
|
dma_axi64_core0_ch_reg_size_wr (
|
.clk(clk),
|
.clk(clk),
|
.reset(reset),
|
.reset(reset),
|
.update(burst_max_size_update),
|
.update(burst_max_size_update),
|
.start_addr(wr_start_addr),
|
.start_addr(wr_start_addr),
|
.burst_max_size_reg(wr_burst_max_size_reg),
|
.burst_max_size_reg(wr_burst_max_size_reg),
|
.burst_max_size_other(rd_burst_max_size_reg),
|
.burst_max_size_other(rd_burst_max_size_reg),
|
.allow_full_burst(1'b0),
|
.allow_full_burst(1'b0),
|
.allow_full_fifo(allow_full_fifo),
|
.allow_full_fifo(allow_full_fifo),
|
.joint_flush(joint_flush),
|
.joint_flush(joint_flush),
|
.burst_max_size(wr_burst_max_size_pre)
|
.burst_max_size(wr_burst_max_size_pre)
|
);
|
);
|
|
|
|
|
always @(posedge clk or posedge reset)
|
always @(posedge clk or posedge reset)
|
if (reset)
|
if (reset)
|
begin
|
begin
|
joint_reg <= #1 1'b1;
|
joint_reg <= #1 1'b1;
|
end_swap_reg <= #1 2'b00;
|
end_swap_reg <= #1 2'b00;
|
end
|
end
|
else if (wr_static_line2)
|
else if (wr_static_line2)
|
begin
|
begin
|
joint_reg <= #1 pwdata[16];
|
joint_reg <= #1 pwdata[16];
|
end_swap_reg <= #1 pwdata[29:28];
|
end_swap_reg <= #1 pwdata[29:28];
|
end
|
end
|
|
|
|
|
always @(posedge clk or posedge reset)
|
always @(posedge clk or posedge reset)
|
if (reset)
|
if (reset)
|
simple_mem <= #1 1'b0;
|
simple_mem <= #1 1'b0;
|
else if (ch_update)
|
else if (ch_update)
|
simple_mem <= #1 (rd_periph_num == 'd0) & (wr_periph_num == 'd0) & (~allow_line_cmd);
|
simple_mem <= #1 (rd_periph_num == 'd0) & (wr_periph_num == 'd0) & (~allow_line_cmd);
|
|
|
assign joint = joint_mode & joint_reg & simple_mem & 1'b1;
|
assign joint = joint_mode & joint_reg & simple_mem & 1'b1;
|
|
|
assign joint_mux = joint;
|
assign joint_mux = joint;
|
|
|
|
|
|
|
assign cmd_port_num = 1'b0;
|
assign cmd_port_num = 1'b0;
|
assign rd_port_num_cfg = 1'b0;
|
assign rd_port_num_cfg = 1'b0;
|
assign wr_port_num = 1'b0;
|
assign wr_port_num = 1'b0;
|
assign rd_port_num = 1'b0;
|
assign rd_port_num = 1'b0;
|
|
|
|
|
assign frame_width = {`FRAME_BITS{1'b0}};
|
assign frame_width = {`FRAME_BITS{1'b0}};
|
assign block = 1'b0;
|
assign block = 1'b0;
|
|
|
assign width_align = frame_width[3-1:0];
|
assign width_align = frame_width[3-1:0];
|
|
|
|
|
assign rd_wait_limit = {`WAIT_BITS-4{1'b0}};
|
assign rd_wait_limit = {`WAIT_BITS-4{1'b0}};
|
assign wr_wait_limit = {`WAIT_BITS-4{1'b0}};
|
assign wr_wait_limit = {`WAIT_BITS-4{1'b0}};
|
|
|
|
|
|
|
always @(posedge clk or posedge reset)
|
always @(posedge clk or posedge reset)
|
if (reset)
|
if (reset)
|
begin
|
begin
|
rd_periph_num_reg <= #1 'd0; //0 is memory
|
rd_periph_num_reg <= #1 'd0; //0 is memory
|
rd_periph_delay_reg <= #1 'd0; //0 is memory
|
rd_periph_delay_reg <= #1 'd0; //0 is memory
|
wr_periph_num_reg <= #1 'd0; //0 is memory
|
wr_periph_num_reg <= #1 'd0; //0 is memory
|
wr_periph_delay_reg <= #1 'd0; //0 is memory
|
wr_periph_delay_reg <= #1 'd0; //0 is memory
|
end
|
end
|
else if (wr_static_line4)
|
else if (wr_static_line4)
|
begin
|
begin
|
rd_periph_num_reg <= #1 pwdata[4:0];
|
rd_periph_num_reg <= #1 pwdata[4:0];
|
rd_periph_delay_reg <= #1 pwdata[`DELAY_BITS+8-1:8];
|
rd_periph_delay_reg <= #1 pwdata[`DELAY_BITS+8-1:8];
|
wr_periph_num_reg <= #1 pwdata[20:16];
|
wr_periph_num_reg <= #1 pwdata[20:16];
|
wr_periph_delay_reg <= #1 pwdata[`DELAY_BITS+24-1:24];
|
wr_periph_delay_reg <= #1 pwdata[`DELAY_BITS+24-1:24];
|
end
|
end
|
|
|
assign rd_periph_num = rd_periph_num_reg;
|
assign rd_periph_num = rd_periph_num_reg;
|
assign wr_periph_num = wr_periph_num_reg;
|
assign wr_periph_num = wr_periph_num_reg;
|
assign rd_periph_delay = rd_periph_delay_reg;
|
assign rd_periph_delay = rd_periph_delay_reg;
|
assign wr_periph_delay = wr_periph_delay_reg;
|
assign wr_periph_delay = wr_periph_delay_reg;
|
|
|
assign rd_periph_block = 1'b0;
|
assign rd_periph_block = 1'b0;
|
assign wr_periph_block = 1'b0;
|
assign wr_periph_block = 1'b0;
|
|
|
|
|
|
|
always @(posedge clk or posedge reset)
|
always @(posedge clk or posedge reset)
|
if (reset)
|
if (reset)
|
begin
|
begin
|
ch_enable <= #1 1'b1;
|
ch_enable <= #1 1'b1;
|
end
|
end
|
else if (wr_ch_enable)
|
else if (wr_ch_enable)
|
begin
|
begin
|
ch_enable <= #1 pwdata[0];
|
ch_enable <= #1 pwdata[0];
|
end
|
end
|
|
|
always @(posedge clk or posedge reset)
|
always @(posedge clk or posedge reset)
|
if (reset)
|
if (reset)
|
ch_in_prog <= #1 1'b0;
|
ch_in_prog <= #1 1'b0;
|
else if (ch_update)
|
else if (ch_update)
|
ch_in_prog <= #1 1'b1;
|
ch_in_prog <= #1 1'b1;
|
else if (ch_end & clken)
|
else if (ch_end & clken)
|
ch_in_prog <= #1 1'b0;
|
ch_in_prog <= #1 1'b0;
|
|
|
always @(posedge clk or posedge reset)
|
always @(posedge clk or posedge reset)
|
if (reset)
|
if (reset)
|
rd_ch_in_prog <= #1 1'b0;
|
rd_ch_in_prog <= #1 1'b0;
|
else if (ch_update)
|
else if (ch_update)
|
rd_ch_in_prog <= #1 1'b1;
|
rd_ch_in_prog <= #1 1'b1;
|
else if (fifo_underflow | fifo_overflow)
|
else if (fifo_underflow | fifo_overflow)
|
rd_ch_in_prog <= #1 1'b0;
|
rd_ch_in_prog <= #1 1'b0;
|
else if (rd_ch_end & clken)
|
else if (rd_ch_end & clken)
|
rd_ch_in_prog <= #1 1'b0;
|
rd_ch_in_prog <= #1 1'b0;
|
|
|
always @(posedge clk or posedge reset)
|
always @(posedge clk or posedge reset)
|
if (reset)
|
if (reset)
|
wr_ch_in_prog <= #1 1'b0;
|
wr_ch_in_prog <= #1 1'b0;
|
else if (ch_update)
|
else if (ch_update)
|
wr_ch_in_prog <= #1 1'b1;
|
wr_ch_in_prog <= #1 1'b1;
|
else if (fifo_underflow | fifo_overflow)
|
else if (fifo_underflow | fifo_overflow)
|
wr_ch_in_prog <= #1 1'b0;
|
wr_ch_in_prog <= #1 1'b0;
|
else if (wr_ch_end & clken)
|
else if (wr_ch_end & clken)
|
wr_ch_in_prog <= #1 1'b0;
|
wr_ch_in_prog <= #1 1'b0;
|
|
|
always @(posedge clk or posedge reset)
|
always @(posedge clk or posedge reset)
|
if (reset)
|
if (reset)
|
load_in_prog_reg <= #1 1'b0;
|
load_in_prog_reg <= #1 1'b0;
|
else if (load_req & clken)
|
else if (load_req & clken)
|
load_in_prog_reg <= #1 1'b1;
|
load_in_prog_reg <= #1 1'b1;
|
else if (ch_update & clken)
|
else if (ch_update & clken)
|
load_in_prog_reg <= #1 1'b0;
|
load_in_prog_reg <= #1 1'b0;
|
|
|
always @(posedge clk or posedge reset)
|
always @(posedge clk or posedge reset)
|
if (reset)
|
if (reset)
|
load_req_in_prog_reg <= #1 1'b0;
|
load_req_in_prog_reg <= #1 1'b0;
|
else if (load_req & clken)
|
else if (load_req & clken)
|
load_req_in_prog_reg <= #1 1'b1;
|
load_req_in_prog_reg <= #1 1'b1;
|
else if (load_cmd & clken)
|
else if (load_cmd & clken)
|
load_req_in_prog_reg <= #1 1'b0;
|
load_req_in_prog_reg <= #1 1'b0;
|
|
|
assign load_in_prog = load_in_prog_reg;
|
assign load_in_prog = load_in_prog_reg;
|
assign load_req_in_prog = load_req_in_prog_reg;
|
assign load_req_in_prog = load_req_in_prog_reg;
|
|
|
assign auto_retry = 1'b0;
|
assign auto_retry = 1'b0;
|
assign ch_retry_wait = 1'b0;
|
assign ch_retry_wait = 1'b0;
|
assign ch_retry = 1'b0;
|
assign ch_retry = 1'b0;
|
|
|
assign ch_update_pre = wr_ch_start | load_wr_last | ch_retry;
|
assign ch_update_pre = wr_ch_start | load_wr_last | ch_retry;
|
|
|
always @(posedge clk or posedge reset)
|
always @(posedge clk or posedge reset)
|
if (reset)
|
if (reset)
|
ch_update <= #1 1'b0;
|
ch_update <= #1 1'b0;
|
else if (ch_update_pre)
|
else if (ch_update_pre)
|
ch_update <= #1 1'b1;
|
ch_update <= #1 1'b1;
|
else if (clken)
|
else if (clken)
|
ch_update <= #1 1'b0;
|
ch_update <= #1 1'b0;
|
|
|
prgen_delay #(1) delay_ch_update (.clk(clk), .reset(reset), .din(ch_update), .dout(ch_update_d));
|
prgen_delay #(1) delay_ch_update (.clk(clk), .reset(reset), .din(ch_update), .dout(ch_update_d));
|
|
|
assign load_req = (ch_enable & ch_end & (~cmd_last)) | (ch_update & (x_size == 'd0));
|
assign load_req = (ch_enable & ch_end & (~cmd_last)) | (ch_update & (x_size == 'd0));
|
assign load_addr = {cmd_next_addr[32-1:2], 2'b00};
|
assign load_addr = {cmd_next_addr[32-1:2], 2'b00};
|
|
|
assign ch_end = rd_ch_end & wr_ch_end & wr_clr_last & (~ch_retry_wait);
|
assign ch_end = rd_ch_end & wr_ch_end & wr_clr_last & (~ch_retry_wait);
|
|
|
assign ch_end_int = ch_enable & ch_end & cmd_set_int;
|
assign ch_end_int = ch_enable & ch_end & cmd_set_int;
|
assign ch_rd_active = ch_enable & (rd_ch_in_prog | load_req_in_prog);
|
assign ch_rd_active = ch_enable & (rd_ch_in_prog | load_req_in_prog);
|
assign ch_wr_active = ch_enable & wr_ch_in_prog;
|
assign ch_wr_active = ch_enable & wr_ch_in_prog;
|
|
|
assign ch_end_set = |int_counter;
|
assign ch_end_set = |int_counter;
|
assign ch_end_clear = wr_int_clear & pwdata[0];
|
assign ch_end_clear = wr_int_clear & pwdata[0];
|
|
|
assign {timeout_aw,
|
assign {timeout_aw,
|
timeout_w,
|
timeout_w,
|
timeout_b,
|
timeout_b,
|
timeout_ar,
|
timeout_ar,
|
timeout_r} = timeout_bus[4:0];
|
timeout_r} = timeout_bus[4:0];
|
|
|
|
|
|
|
assign int_bus = {INT_NUM{clken}} & {
|
assign int_bus = {INT_NUM{clken}} & {
|
wdt_timeout,
|
wdt_timeout,
|
timeout_aw,
|
timeout_aw,
|
timeout_w,
|
timeout_w,
|
timeout_b,
|
timeout_b,
|
timeout_ar,
|
timeout_ar,
|
timeout_r,
|
timeout_r,
|
fifo_underflow,
|
fifo_underflow,
|
fifo_overflow,
|
fifo_overflow,
|
wr_decerr,
|
wr_decerr,
|
rd_decerr,
|
rd_decerr,
|
wr_slverr,
|
wr_slverr,
|
rd_slverr,
|
rd_slverr,
|
ch_end_set
|
ch_end_set
|
};
|
};
|
|
|
prgen_rawstat #(INT_NUM) rawstat(
|
prgen_rawstat #(INT_NUM) rawstat(
|
.clk(clk),
|
.clk(clk),
|
.reset(reset),
|
.reset(reset),
|
.clear(wr_int_clear),
|
.clear(wr_int_clear),
|
.write(wr_int_rawstat),
|
.write(wr_int_rawstat),
|
.pwdata(pwdata[INT_NUM-1:0]),
|
.pwdata(pwdata[INT_NUM-1:0]),
|
.int_bus(int_bus),
|
.int_bus(int_bus),
|
.rawstat(int_rawstat)
|
.rawstat(int_rawstat)
|
);
|
);
|
|
|
|
|
always @(posedge clk or posedge reset)
|
always @(posedge clk or posedge reset)
|
if (reset)
|
if (reset)
|
int_enable <= #1 {INT_NUM{1'b1}};
|
int_enable <= #1 {INT_NUM{1'b1}};
|
else if (wr_int_enable)
|
else if (wr_int_enable)
|
int_enable <= #1 pwdata[INT_NUM-1:0];
|
int_enable <= #1 pwdata[INT_NUM-1:0];
|
|
|
assign int_status = int_rawstat & int_enable;
|
assign int_status = int_rawstat & int_enable;
|
|
|
assign ch_int = |int_status;
|
assign ch_int = |int_status;
|
|
|
assign int_proc_num = 3'd0;
|
assign int_proc_num = 3'd0;
|
assign int_all_proc = ch_int;
|
assign int_all_proc = ch_int;
|
|
|
assign end_swap = end_swap_reg;
|
assign end_swap = end_swap_reg;
|
|
|
//---------------------- Read Operations -----------------------------------
|
//---------------------- Read Operations -----------------------------------
|
assign rd_burst_max_size_rd = rd_burst_max_size_reg;
|
assign rd_burst_max_size_rd = rd_burst_max_size_reg;
|
assign wr_burst_max_size_rd = wr_burst_max_size_reg;
|
assign wr_burst_max_size_rd = wr_burst_max_size_reg;
|
|
|
|
|
//always @(/*AUTOSENSE*/) - no AUTOSENSE because of include file
|
//always @(/*AUTOSENSE*/) - no AUTOSENSE because of include file
|
always @(allow_full_burst or allow_full_fifo
|
always @(allow_full_burst or allow_full_fifo
|
or allow_joint_burst or allow_line_cmd or auto_retry
|
or allow_joint_burst or allow_line_cmd or auto_retry
|
or block or buff_size or ch_enable or ch_rd_active
|
or block or buff_size or ch_enable or ch_rd_active
|
or ch_wr_active or cmd_counter or cmd_last
|
or ch_wr_active or cmd_counter or cmd_last
|
or cmd_next_addr or cmd_port_num or cmd_set_int
|
or cmd_next_addr or cmd_port_num or cmd_set_int
|
or end_swap or frame_width or int_counter or int_enable
|
or end_swap or frame_width or int_counter or int_enable
|
or int_proc_num or int_rawstat or int_status or joint_reg
|
or int_proc_num or int_rawstat or int_status or joint_reg
|
or rd_allow_full_fifo or rd_burst_max_size_rd or rd_gap
|
or rd_allow_full_fifo or rd_burst_max_size_rd or rd_gap
|
or rd_incr or rd_outs or rd_outs_max or rd_outstanding
|
or rd_incr or rd_outs or rd_outs_max or rd_outstanding
|
or rd_outstanding_cfg or rd_periph_block_reg
|
or rd_outstanding_cfg or rd_periph_block_reg
|
or rd_periph_delay or rd_periph_num or rd_port_num_cfg
|
or rd_periph_delay or rd_periph_num or rd_port_num_cfg
|
or rd_start_addr or rd_tokens or rd_wait_limit
|
or rd_start_addr or rd_tokens or rd_wait_limit
|
or rd_x_offset or rd_y_offset or simple_mem
|
or rd_x_offset or rd_y_offset or simple_mem
|
or wr_allow_full_fifo or wr_burst_max_size_rd
|
or wr_allow_full_fifo or wr_burst_max_size_rd
|
or wr_fullness or wr_incr or wr_outs or wr_outs_max
|
or wr_fullness or wr_incr or wr_outs or wr_outs_max
|
or wr_outstanding or wr_outstanding_cfg
|
or wr_outstanding or wr_outstanding_cfg
|
or wr_periph_block_reg or wr_periph_delay or wr_periph_num
|
or wr_periph_block_reg or wr_periph_delay or wr_periph_num
|
or wr_port_num or wr_start_addr or wr_tokens
|
or wr_port_num or wr_start_addr or wr_tokens
|
or wr_wait_limit or wr_x_offset or wr_y_offset)
|
or wr_wait_limit or wr_x_offset or wr_y_offset)
|
begin
|
begin
|
rd_cmd_line0 = {32{1'b0}};
|
rd_cmd_line0 = {32{1'b0}};
|
rd_cmd_line1 = {32{1'b0}};
|
rd_cmd_line1 = {32{1'b0}};
|
rd_cmd_line2 = {32{1'b0}};
|
rd_cmd_line2 = {32{1'b0}};
|
rd_cmd_line3 = {32{1'b0}};
|
rd_cmd_line3 = {32{1'b0}};
|
rd_static_line0 = {32{1'b0}};
|
rd_static_line0 = {32{1'b0}};
|
rd_static_line1 = {32{1'b0}};
|
rd_static_line1 = {32{1'b0}};
|
rd_static_line2 = {32{1'b0}};
|
rd_static_line2 = {32{1'b0}};
|
rd_static_line3 = {32{1'b0}};
|
rd_static_line3 = {32{1'b0}};
|
rd_static_line4 = {32{1'b0}};
|
rd_static_line4 = {32{1'b0}};
|
rd_restrict = {32{1'b0}};
|
rd_restrict = {32{1'b0}};
|
rd_rd_offsets = {32{1'b0}};
|
rd_rd_offsets = {32{1'b0}};
|
rd_wr_offsets = {32{1'b0}};
|
rd_wr_offsets = {32{1'b0}};
|
rd_fifo_fullness = {32{1'b0}};
|
rd_fifo_fullness = {32{1'b0}};
|
rd_cmd_outs = {32{1'b0}};
|
rd_cmd_outs = {32{1'b0}};
|
rd_ch_enable = {32{1'b0}};
|
rd_ch_enable = {32{1'b0}};
|
rd_ch_active = {32{1'b0}};
|
rd_ch_active = {32{1'b0}};
|
rd_cmd_counter = {32{1'b0}};
|
rd_cmd_counter = {32{1'b0}};
|
rd_int_rawstat = {32{1'b0}};
|
rd_int_rawstat = {32{1'b0}};
|
rd_int_enable = {32{1'b0}};
|
rd_int_enable = {32{1'b0}};
|
rd_int_status = {32{1'b0}};
|
rd_int_status = {32{1'b0}};
|
|
|
|
|
rd_cmd_line0[32-1:0] = rd_start_addr;
|
rd_cmd_line0[32-1:0] = rd_start_addr;
|
|
|
rd_cmd_line1[32-1:0] = wr_start_addr;
|
rd_cmd_line1[32-1:0] = wr_start_addr;
|
|
|
rd_cmd_line2[10-1:0] = buff_size;
|
rd_cmd_line2[10-1:0] = buff_size;
|
|
|
rd_cmd_line3[0] = cmd_set_int;
|
rd_cmd_line3[0] = cmd_set_int;
|
rd_cmd_line3[1] = cmd_last;
|
rd_cmd_line3[1] = cmd_last;
|
rd_cmd_line3[32-1:2] = cmd_next_addr;
|
rd_cmd_line3[32-1:2] = cmd_next_addr;
|
|
|
rd_static_line0[8-1:0] = rd_burst_max_size_rd;
|
rd_static_line0[8-1:0] = rd_burst_max_size_rd;
|
rd_static_line0[`TOKEN_BITS+16-1:16] = rd_tokens;
|
rd_static_line0[`TOKEN_BITS+16-1:16] = rd_tokens;
|
rd_static_line0[`OUT_BITS+24-1:24] = rd_outs_max;
|
rd_static_line0[`OUT_BITS+24-1:24] = rd_outs_max;
|
rd_static_line0[30] = rd_outstanding_cfg;
|
rd_static_line0[30] = rd_outstanding_cfg;
|
rd_static_line0[31] = rd_incr;
|
rd_static_line0[31] = rd_incr;
|
|
|
rd_static_line1[8-1:0] = wr_burst_max_size_rd;
|
rd_static_line1[8-1:0] = wr_burst_max_size_rd;
|
rd_static_line1[`TOKEN_BITS+16-1:16] = wr_tokens;
|
rd_static_line1[`TOKEN_BITS+16-1:16] = wr_tokens;
|
rd_static_line1[`OUT_BITS+24-1:24] = wr_outs_max;
|
rd_static_line1[`OUT_BITS+24-1:24] = wr_outs_max;
|
rd_static_line1[30] = wr_outstanding_cfg;
|
rd_static_line1[30] = wr_outstanding_cfg;
|
rd_static_line1[31] = wr_incr;
|
rd_static_line1[31] = wr_incr;
|
|
|
rd_static_line2[`FRAME_BITS-1:0] = frame_width;
|
rd_static_line2[`FRAME_BITS-1:0] = frame_width;
|
rd_static_line2[15] = block;
|
rd_static_line2[15] = block;
|
rd_static_line2[16] = joint_reg;
|
rd_static_line2[16] = joint_reg;
|
rd_static_line2[17] = auto_retry;
|
rd_static_line2[17] = auto_retry;
|
rd_static_line2[20] = cmd_port_num;
|
rd_static_line2[20] = cmd_port_num;
|
rd_static_line2[21] = rd_port_num_cfg;
|
rd_static_line2[21] = rd_port_num_cfg;
|
rd_static_line2[22] = wr_port_num;
|
rd_static_line2[22] = wr_port_num;
|
rd_static_line2[26:24] = int_proc_num;
|
rd_static_line2[26:24] = int_proc_num;
|
rd_static_line2[29:28] = end_swap;
|
rd_static_line2[29:28] = end_swap;
|
|
|
|
|
rd_static_line4[4:0] = rd_periph_num;
|
rd_static_line4[4:0] = rd_periph_num;
|
rd_static_line4[`DELAY_BITS+8-1:8] = rd_periph_delay;
|
rd_static_line4[`DELAY_BITS+8-1:8] = rd_periph_delay;
|
rd_static_line4[20:16] = wr_periph_num;
|
rd_static_line4[20:16] = wr_periph_num;
|
rd_static_line4[`DELAY_BITS+24-1:24] = wr_periph_delay;
|
rd_static_line4[`DELAY_BITS+24-1:24] = wr_periph_delay;
|
|
|
rd_restrict[0] = rd_allow_full_fifo;
|
rd_restrict[0] = rd_allow_full_fifo;
|
rd_restrict[1] = wr_allow_full_fifo;
|
rd_restrict[1] = wr_allow_full_fifo;
|
rd_restrict[2] = allow_full_fifo;
|
rd_restrict[2] = allow_full_fifo;
|
rd_restrict[3] = allow_full_burst;
|
rd_restrict[3] = allow_full_burst;
|
rd_restrict[4] = allow_joint_burst;
|
rd_restrict[4] = allow_joint_burst;
|
rd_restrict[5] = rd_outstanding;
|
rd_restrict[5] = rd_outstanding;
|
rd_restrict[6] = wr_outstanding;
|
rd_restrict[6] = wr_outstanding;
|
rd_restrict[7] = allow_line_cmd;
|
rd_restrict[7] = allow_line_cmd;
|
rd_restrict[8] = simple_mem;
|
rd_restrict[8] = simple_mem;
|
|
|
rd_rd_offsets[10-1:0] = rd_x_offset;
|
rd_rd_offsets[10-1:0] = rd_x_offset;
|
rd_rd_offsets[10-`X_BITS+16-1:16] = rd_y_offset;
|
rd_rd_offsets[10-`X_BITS+16-1:16] = rd_y_offset;
|
|
|
rd_wr_offsets[10-1:0] = wr_x_offset;
|
rd_wr_offsets[10-1:0] = wr_x_offset;
|
rd_wr_offsets[10-`X_BITS+16-1:16] = wr_y_offset;
|
rd_wr_offsets[10-`X_BITS+16-1:16] = wr_y_offset;
|
|
|
rd_fifo_fullness[5:0] = rd_gap;
|
rd_fifo_fullness[5:0] = rd_gap;
|
rd_fifo_fullness[5+16:16] = wr_fullness;
|
rd_fifo_fullness[5+16:16] = wr_fullness;
|
|
|
rd_cmd_outs[`OUT_BITS-1:0] = rd_outs;
|
rd_cmd_outs[`OUT_BITS-1:0] = rd_outs;
|
rd_cmd_outs[`OUT_BITS-1+8:8] = wr_outs;
|
rd_cmd_outs[`OUT_BITS-1+8:8] = wr_outs;
|
|
|
rd_ch_enable[0] = ch_enable;
|
rd_ch_enable[0] = ch_enable;
|
|
|
rd_ch_active[0] = ch_rd_active;
|
rd_ch_active[0] = ch_rd_active;
|
rd_ch_active[1] = ch_wr_active;
|
rd_ch_active[1] = ch_wr_active;
|
|
|
rd_cmd_counter[`CMD_CNT_BITS-1:0] = cmd_counter;
|
rd_cmd_counter[`CMD_CNT_BITS-1:0] = cmd_counter;
|
rd_cmd_counter[`INT_CNT_BITS-1+16:16] = int_counter;
|
rd_cmd_counter[`INT_CNT_BITS-1+16:16] = int_counter;
|
|
|
rd_int_rawstat[INT_NUM-1:0] = int_rawstat;
|
rd_int_rawstat[INT_NUM-1:0] = int_rawstat;
|
|
|
rd_int_enable[INT_NUM-1:0] = int_enable;
|
rd_int_enable[INT_NUM-1:0] = int_enable;
|
|
|
rd_int_status[INT_NUM-1:0] = int_status;
|
rd_int_status[INT_NUM-1:0] = int_status;
|
end
|
end
|
|
|
|
|
//always @(/*AUTOSENSE*/) - no AUTOSENSE because of include file
|
//always @(/*AUTOSENSE*/) - no AUTOSENSE because of include file
|
always @(gpaddr or rd_ch_active or rd_ch_enable
|
always @(gpaddr or rd_ch_active or rd_ch_enable
|
or rd_cmd_counter or rd_cmd_line0 or rd_cmd_line1
|
or rd_cmd_counter or rd_cmd_line0 or rd_cmd_line1
|
or rd_cmd_line2 or rd_cmd_line3 or rd_cmd_outs
|
or rd_cmd_line2 or rd_cmd_line3 or rd_cmd_outs
|
or rd_fifo_fullness or rd_int_enable or rd_int_rawstat
|
or rd_fifo_fullness or rd_int_enable or rd_int_rawstat
|
or rd_int_status or rd_rd_offsets or rd_restrict
|
or rd_int_status or rd_rd_offsets or rd_restrict
|
or rd_static_line0 or rd_static_line1 or rd_static_line2
|
or rd_static_line0 or rd_static_line1 or rd_static_line2
|
or rd_static_line3 or rd_static_line4 or rd_wr_offsets)
|
or rd_static_line3 or rd_static_line4 or rd_wr_offsets)
|
begin
|
begin
|
prdata_pre = {32{1'b0}};
|
prdata_pre = {32{1'b0}};
|
|
|
case (gpaddr)
|
case (gpaddr)
|
CMD_LINE0 : prdata_pre = rd_cmd_line0;
|
CMD_LINE0 : prdata_pre = rd_cmd_line0;
|
CMD_LINE1 : prdata_pre = rd_cmd_line1;
|
CMD_LINE1 : prdata_pre = rd_cmd_line1;
|
CMD_LINE2 : prdata_pre = rd_cmd_line2;
|
CMD_LINE2 : prdata_pre = rd_cmd_line2;
|
CMD_LINE3 : prdata_pre = rd_cmd_line3;
|
CMD_LINE3 : prdata_pre = rd_cmd_line3;
|
|
|
STATIC_LINE0 : prdata_pre = rd_static_line0;
|
STATIC_LINE0 : prdata_pre = rd_static_line0;
|
STATIC_LINE1 : prdata_pre = rd_static_line1;
|
STATIC_LINE1 : prdata_pre = rd_static_line1;
|
STATIC_LINE2 : prdata_pre = rd_static_line2;
|
STATIC_LINE2 : prdata_pre = rd_static_line2;
|
STATIC_LINE3 : prdata_pre = rd_static_line3;
|
STATIC_LINE3 : prdata_pre = rd_static_line3;
|
STATIC_LINE4 : prdata_pre = rd_static_line4;
|
STATIC_LINE4 : prdata_pre = rd_static_line4;
|
|
|
RESTRICT : prdata_pre = rd_restrict;
|
RESTRICT : prdata_pre = rd_restrict;
|
RD_OFFSETS : prdata_pre = rd_rd_offsets;
|
RD_OFFSETS : prdata_pre = rd_rd_offsets;
|
WR_OFFSETS : prdata_pre = rd_wr_offsets;
|
WR_OFFSETS : prdata_pre = rd_wr_offsets;
|
FIFO_FULLNESS : prdata_pre = rd_fifo_fullness;
|
FIFO_FULLNESS : prdata_pre = rd_fifo_fullness;
|
CMD_OUTS : prdata_pre = rd_cmd_outs;
|
CMD_OUTS : prdata_pre = rd_cmd_outs;
|
|
|
CH_ENABLE : prdata_pre = rd_ch_enable;
|
CH_ENABLE : prdata_pre = rd_ch_enable;
|
CH_START : prdata_pre = {32{1'b0}};
|
CH_START : prdata_pre = {32{1'b0}};
|
CH_ACTIVE : prdata_pre = rd_ch_active;
|
CH_ACTIVE : prdata_pre = rd_ch_active;
|
CH_CMD_COUNTER : prdata_pre = rd_cmd_counter;
|
CH_CMD_COUNTER : prdata_pre = rd_cmd_counter;
|
|
|
INT_RAWSTAT : prdata_pre = rd_int_rawstat;
|
INT_RAWSTAT : prdata_pre = rd_int_rawstat;
|
INT_CLEAR : prdata_pre = {32{1'b0}};
|
INT_CLEAR : prdata_pre = {32{1'b0}};
|
INT_ENABLE : prdata_pre = rd_int_enable;
|
INT_ENABLE : prdata_pre = rd_int_enable;
|
INT_STATUS : prdata_pre = rd_int_status;
|
INT_STATUS : prdata_pre = rd_int_status;
|
|
|
default : prdata_pre = {32{1'b0}};
|
default : prdata_pre = {32{1'b0}};
|
endcase
|
endcase
|
end
|
end
|
|
|
|
|
//always @(/*AUTOSENSE*/) - no AUTOSENSE because of include file
|
//always @(/*AUTOSENSE*/) - no AUTOSENSE because of include file
|
always @(gpaddr or gpread or gpwrite or psel)
|
always @(gpaddr or gpread or gpwrite or psel)
|
begin
|
begin
|
pslverr_pre = 1'b0;
|
pslverr_pre = 1'b0;
|
|
|
case (gpaddr)
|
case (gpaddr)
|
CMD_LINE0 : pslverr_pre = 1'b0; //read and write
|
CMD_LINE0 : pslverr_pre = 1'b0; //read and write
|
CMD_LINE1 : pslverr_pre = 1'b0; //read and write
|
CMD_LINE1 : pslverr_pre = 1'b0; //read and write
|
CMD_LINE2 : pslverr_pre = 1'b0; //read and write
|
CMD_LINE2 : pslverr_pre = 1'b0; //read and write
|
CMD_LINE3 : pslverr_pre = 1'b0; //read and write
|
CMD_LINE3 : pslverr_pre = 1'b0; //read and write
|
|
|
STATIC_LINE0 : pslverr_pre = 1'b0; //read and write
|
STATIC_LINE0 : pslverr_pre = 1'b0; //read and write
|
STATIC_LINE1 : pslverr_pre = 1'b0; //read and write
|
STATIC_LINE1 : pslverr_pre = 1'b0; //read and write
|
STATIC_LINE2 : pslverr_pre = 1'b0; //read and write
|
STATIC_LINE2 : pslverr_pre = 1'b0; //read and write
|
STATIC_LINE3 : pslverr_pre = 1'b0; //read and write
|
STATIC_LINE3 : pslverr_pre = 1'b0; //read and write
|
STATIC_LINE4 : pslverr_pre = 1'b0; //read and write
|
STATIC_LINE4 : pslverr_pre = 1'b0; //read and write
|
|
|
RESTRICT : pslverr_pre = gpwrite; //read only
|
RESTRICT : pslverr_pre = gpwrite; //read only
|
RD_OFFSETS : pslverr_pre = gpwrite; //read only
|
RD_OFFSETS : pslverr_pre = gpwrite; //read only
|
WR_OFFSETS : pslverr_pre = gpwrite; //read only
|
WR_OFFSETS : pslverr_pre = gpwrite; //read only
|
FIFO_FULLNESS : pslverr_pre = gpwrite; //read only
|
FIFO_FULLNESS : pslverr_pre = gpwrite; //read only
|
CMD_OUTS : pslverr_pre = gpwrite; //read only
|
CMD_OUTS : pslverr_pre = gpwrite; //read only
|
|
|
CH_ENABLE : pslverr_pre = 1'b0; //read and write
|
CH_ENABLE : pslverr_pre = 1'b0; //read and write
|
CH_START : pslverr_pre = gpread; //write only
|
CH_START : pslverr_pre = gpread; //write only
|
CH_ACTIVE : pslverr_pre = gpwrite; //read only
|
CH_ACTIVE : pslverr_pre = gpwrite; //read only
|
CH_CMD_COUNTER : pslverr_pre = gpwrite; //read only
|
CH_CMD_COUNTER : pslverr_pre = gpwrite; //read only
|
|
|
INT_RAWSTAT : pslverr_pre = 1'b0; //read and write
|
INT_RAWSTAT : pslverr_pre = 1'b0; //read and write
|
INT_CLEAR : pslverr_pre = gpread; //write only
|
INT_CLEAR : pslverr_pre = gpread; //write only
|
INT_ENABLE : pslverr_pre = 1'b0; //read and write
|
INT_ENABLE : pslverr_pre = 1'b0; //read and write
|
INT_STATUS : pslverr_pre = gpwrite; //read only
|
INT_STATUS : pslverr_pre = gpwrite; //read only
|
|
|
default : pslverr_pre = psel; //decode error
|
default : pslverr_pre = psel; //decode error
|
endcase
|
endcase
|
end
|
end
|
|
|
always @(posedge clk or posedge reset)
|
always @(posedge clk or posedge reset)
|
if (reset)
|
if (reset)
|
prdata <= #1 {32{1'b0}};
|
prdata <= #1 {32{1'b0}};
|
else if (gpread & pclken)
|
else if (gpread & pclken)
|
prdata <= #1 prdata_pre;
|
prdata <= #1 prdata_pre;
|
else if (pclken)
|
else if (pclken)
|
prdata <= #1 {32{1'b0}};
|
prdata <= #1 {32{1'b0}};
|
|
|
always @(posedge clk or posedge reset)
|
always @(posedge clk or posedge reset)
|
if (reset)
|
if (reset)
|
pslverr <= #1 1'b0;
|
pslverr <= #1 1'b0;
|
else if ((gpread | gpwrite) & pclken)
|
else if ((gpread | gpwrite) & pclken)
|
pslverr <= #1 pslverr_pre;
|
pslverr <= #1 pslverr_pre;
|
else if (pclken)
|
else if (pclken)
|
pslverr <= #1 1'b0;
|
pslverr <= #1 1'b0;
|
|
|
|
|
|
|
endmodule
|
endmodule
|
|
|
|
|
|
|