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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Author: Eyal Hochberg ////
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//// eyal@provartec.com ////
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//// ////
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//// Downloaded from: http://www.opencores.org ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2010 Provartec LTD ////
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//// www.provartec.com ////
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//// info@provartec.com ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation.////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more////
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//// details. http://www.gnu.org/licenses/lgpl.html ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//---------------------------------------------------------
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//---------------------------------------------------------
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//-- File generated by RobustVerilog parser
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//-- File generated by RobustVerilog parser
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//-- Version: 1.0
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//-- Version: 1.0
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//-- Invoked Fri Mar 25 23:36:56 2011
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//-- Invoked Fri Mar 25 23:36:56 2011
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//--
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//--
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//-- Source file: dma_ch_remain.v
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//-- Source file: dma_ch_remain.v
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//---------------------------------------------------------
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//---------------------------------------------------------
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module dma_axi64_core0_ch_remain(clk,reset,ch_update,wr_outstanding,rd_outstanding,load_req_in_prog,rd_line_cmd,rd_burst_start,rd_burst_size,rd_transfer,rd_transfer_size,wr_clr_line,wr_burst_start,wr_burst_size,wr_transfer,wr_transfer_size,rd_gap,wr_fullness);
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module dma_axi64_core0_ch_remain(clk,reset,ch_update,wr_outstanding,rd_outstanding,load_req_in_prog,rd_line_cmd,rd_burst_start,rd_burst_size,rd_transfer,rd_transfer_size,wr_clr_line,wr_burst_start,wr_burst_size,wr_transfer,wr_transfer_size,rd_gap,wr_fullness);
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input clk;
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input clk;
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input reset;
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input reset;
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input ch_update;
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input ch_update;
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input wr_outstanding;
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input wr_outstanding;
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input rd_outstanding;
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input rd_outstanding;
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input load_req_in_prog;
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input load_req_in_prog;
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input rd_line_cmd;
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input rd_line_cmd;
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input rd_burst_start;
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input rd_burst_start;
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input [8-1:0] rd_burst_size;
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input [8-1:0] rd_burst_size;
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input rd_transfer;
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input rd_transfer;
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input [4-1:0] rd_transfer_size;
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input [4-1:0] rd_transfer_size;
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input wr_clr_line;
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input wr_clr_line;
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input wr_burst_start;
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input wr_burst_start;
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input [8-1:0] wr_burst_size;
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input [8-1:0] wr_burst_size;
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input wr_transfer;
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input wr_transfer;
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input [4-1:0] wr_transfer_size;
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input [4-1:0] wr_transfer_size;
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output [5:0] rd_gap;
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output [5:0] rd_gap;
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output [5:0] wr_fullness;
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output [5:0] wr_fullness;
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wire rd_line_cmd_valid;
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wire rd_line_cmd_valid;
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reg [5+1:0] rd_gap_reg; //signed
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reg [5+1:0] rd_gap_reg; //signed
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reg [5+1:0] wr_fullness_reg; //signed
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reg [5+1:0] wr_fullness_reg; //signed
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wire rd_burst_qual;
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wire rd_burst_qual;
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wire wr_burst_qual;
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wire wr_burst_qual;
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reg [8-1:0] rd_burst_size_valid;
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reg [8-1:0] rd_burst_size_valid;
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wire [4-1:0] rd_transfer_size_valid;
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wire [4-1:0] rd_transfer_size_valid;
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wire [4-1:0] wr_transfer_size_valid;
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wire [4-1:0] wr_transfer_size_valid;
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reg [8-1:0] wr_burst_size_valid;
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reg [8-1:0] wr_burst_size_valid;
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assign rd_line_cmd_valid = rd_line_cmd & rd_burst_start;
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assign rd_line_cmd_valid = rd_line_cmd & rd_burst_start;
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assign rd_burst_qual = rd_burst_start & (~load_req_in_prog);
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assign rd_burst_qual = rd_burst_start & (~load_req_in_prog);
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assign wr_burst_qual = wr_burst_start;
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assign wr_burst_qual = wr_burst_start;
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always @(posedge clk or posedge reset)
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always @(posedge clk or posedge reset)
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if (reset)
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if (reset)
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rd_burst_size_valid <= #1 {8{1'b0}};
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rd_burst_size_valid <= #1 {8{1'b0}};
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else if (rd_burst_qual)
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else if (rd_burst_qual)
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rd_burst_size_valid <= #1 rd_burst_size;
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rd_burst_size_valid <= #1 rd_burst_size;
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else
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else
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rd_burst_size_valid <= #1 {8{1'b0}};
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rd_burst_size_valid <= #1 {8{1'b0}};
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always @(posedge clk or posedge reset)
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always @(posedge clk or posedge reset)
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if (reset)
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if (reset)
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wr_burst_size_valid <= #1 {8{1'b0}};
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wr_burst_size_valid <= #1 {8{1'b0}};
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else if (wr_burst_qual)
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else if (wr_burst_qual)
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wr_burst_size_valid <= #1 wr_burst_size;
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wr_burst_size_valid <= #1 wr_burst_size;
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else
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else
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wr_burst_size_valid <= #1 {8{1'b0}};
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wr_burst_size_valid <= #1 {8{1'b0}};
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assign rd_transfer_size_valid = {4{rd_transfer}} & rd_transfer_size;
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assign rd_transfer_size_valid = {4{rd_transfer}} & rd_transfer_size;
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assign wr_transfer_size_valid = {4{wr_transfer}} & wr_transfer_size;
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assign wr_transfer_size_valid = {4{wr_transfer}} & wr_transfer_size;
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//for rd bursts
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//for rd bursts
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always @(posedge clk or posedge reset)
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always @(posedge clk or posedge reset)
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if (reset)
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if (reset)
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rd_gap_reg <= #1 {1'b0, 1'b1, {5{1'b0}}};
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rd_gap_reg <= #1 {1'b0, 1'b1, {5{1'b0}}};
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else if (ch_update)
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else if (ch_update)
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rd_gap_reg <= #1 {1'b0, 1'b1, {5{1'b0}}};
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rd_gap_reg <= #1 {1'b0, 1'b1, {5{1'b0}}};
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else
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else
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rd_gap_reg <= #1 rd_gap_reg -
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rd_gap_reg <= #1 rd_gap_reg -
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rd_burst_size_valid +
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rd_burst_size_valid +
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wr_transfer_size_valid;
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wr_transfer_size_valid;
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assign rd_gap = rd_gap_reg[5+1] ? 'd0 : rd_gap_reg[5:0];
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assign rd_gap = rd_gap_reg[5+1] ? 'd0 : rd_gap_reg[5:0];
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//for wr bursts
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//for wr bursts
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always @(posedge clk or posedge reset)
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always @(posedge clk or posedge reset)
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if (reset)
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if (reset)
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wr_fullness_reg <= #1 {5+1{1'b0}};
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wr_fullness_reg <= #1 {5+1{1'b0}};
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else if (ch_update)
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else if (ch_update)
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wr_fullness_reg <= #1 {5+1{1'b0}};
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wr_fullness_reg <= #1 {5+1{1'b0}};
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else
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else
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wr_fullness_reg <= #1 wr_fullness_reg -
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wr_fullness_reg <= #1 wr_fullness_reg -
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wr_burst_size_valid +
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wr_burst_size_valid +
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rd_transfer_size_valid;
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rd_transfer_size_valid;
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assign wr_fullness = wr_fullness_reg[5+1] ? 'd0 : wr_fullness_reg[5:0];
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assign wr_fullness = wr_fullness_reg[5+1] ? 'd0 : wr_fullness_reg[5:0];
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endmodule
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endmodule
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