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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Author: Eyal Hochberg ////
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//// eyal@provartec.com ////
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//// ////
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//// Downloaded from: http://www.opencores.org ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2010 Provartec LTD ////
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//// www.provartec.com ////
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//// info@provartec.com ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation.////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more////
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//// details. http://www.gnu.org/licenses/lgpl.html ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//---------------------------------------------------------
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//---------------------------------------------------------
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//-- File generated by RobustVerilog parser
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//-- File generated by RobustVerilog parser
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//-- Version: 1.0
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//-- Version: 1.0
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//-- Invoked Fri Mar 25 23:36:55 2011
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//-- Invoked Fri Mar 25 23:36:55 2011
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//--
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//--
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//-- Source file: dma_core_channels_apb_mux.v
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//-- Source file: dma_core_channels_apb_mux.v
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//---------------------------------------------------------
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//---------------------------------------------------------
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module dma_axi64_core0_channels_apb_mux (clk,reset,pclken,psel,penable,paddr,prdata,pslverr,ch_psel,ch_prdata,ch_pslverr);
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module dma_axi64_core0_channels_apb_mux (clk,reset,pclken,psel,penable,paddr,prdata,pslverr,ch_psel,ch_prdata,ch_pslverr);
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input clk;
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input clk;
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input reset;
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input reset;
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input pclken;
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input pclken;
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input psel;
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input psel;
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input penable;
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input penable;
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input [10:8] paddr;
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input [10:8] paddr;
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output [31:0] prdata;
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output [31:0] prdata;
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output pslverr;
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output pslverr;
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output [7:0] ch_psel;
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output [7:0] ch_psel;
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input [32*8-1:0] ch_prdata;
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input [32*8-1:0] ch_prdata;
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input [7:0] ch_pslverr;
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input [7:0] ch_pslverr;
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wire [2:0] paddr_sel;
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wire [2:0] paddr_sel;
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reg [2:0] paddr_sel_d;
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reg [2:0] paddr_sel_d;
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always @(posedge clk or posedge reset)
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always @(posedge clk or posedge reset)
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if (reset)
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if (reset)
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paddr_sel_d <= #1 3'b000;
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paddr_sel_d <= #1 3'b000;
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else if (psel & (~penable))
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else if (psel & (~penable))
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paddr_sel_d <= #1 paddr_sel;
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paddr_sel_d <= #1 paddr_sel;
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else if ((~psel) & pclken) //release for empty channels after error
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else if ((~psel) & pclken) //release for empty channels after error
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paddr_sel_d <= #1 3'b000;
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paddr_sel_d <= #1 3'b000;
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assign paddr_sel = paddr[10:8];
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assign paddr_sel = paddr[10:8];
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prgen_demux8 #(1) mux_psel(
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prgen_demux8 #(1) mux_psel(
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.sel(paddr_sel),
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.sel(paddr_sel),
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.x(psel),
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.x(psel),
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.ch_x(ch_psel)
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.ch_x(ch_psel)
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);
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);
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prgen_mux8 #(32) mux_prdata(
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prgen_mux8 #(32) mux_prdata(
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.sel(paddr_sel_d),
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.sel(paddr_sel_d),
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.ch_x(ch_prdata),
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.ch_x(ch_prdata),
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.x(prdata)
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.x(prdata)
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);
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);
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assign pslverr = ch_pslverr[paddr_sel_d];
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assign pslverr = ch_pslverr[paddr_sel_d];
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endmodule
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endmodule
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