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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Author: Eyal Hochberg ////
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//// eyal@provartec.com ////
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//// ////
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//// Downloaded from: http://www.opencores.org ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2010 Provartec LTD ////
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//// www.provartec.com ////
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//// info@provartec.com ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation.////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more////
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//// details. http://www.gnu.org/licenses/lgpl.html ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//---------------------------------------------------------
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//---------------------------------------------------------
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//-- File generated by RobustVerilog parser
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//-- File generated by RobustVerilog parser
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//-- Version: 1.0
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//-- Version: 1.0
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//-- Invoked Fri Mar 25 23:36:55 2011
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//-- Invoked Fri Mar 25 23:36:55 2011
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//--
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//--
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//-- Source file: prgen_demux.v
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//-- Source file: prgen_demux.v
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//---------------------------------------------------------
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//---------------------------------------------------------
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module prgen_demux8(sel,x,ch_x);
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module prgen_demux8(sel,x,ch_x);
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parameter WIDTH = 8;
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parameter WIDTH = 8;
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input [3-1:0] sel;
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input [3-1:0] sel;
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input [WIDTH-1:0] x;
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input [WIDTH-1:0] x;
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output [8*WIDTH-1:0] ch_x;
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output [8*WIDTH-1:0] ch_x;
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reg [8*WIDTH-1:0] ch_x;
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reg [8*WIDTH-1:0] ch_x;
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always @(/*AUTOSENSE*/sel or x)
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always @(/*AUTOSENSE*/sel or x)
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begin
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begin
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ch_x = {8*WIDTH{1'b0}};
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ch_x = {8*WIDTH{1'b0}};
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case (sel)
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case (sel)
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3'd0 : ch_x[WIDTH-1+WIDTH*0:WIDTH*0] = x;
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3'd0 : ch_x[WIDTH-1+WIDTH*0:WIDTH*0] = x;
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3'd1 : ch_x[WIDTH-1+WIDTH*1:WIDTH*1] = x;
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3'd1 : ch_x[WIDTH-1+WIDTH*1:WIDTH*1] = x;
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3'd2 : ch_x[WIDTH-1+WIDTH*2:WIDTH*2] = x;
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3'd2 : ch_x[WIDTH-1+WIDTH*2:WIDTH*2] = x;
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3'd3 : ch_x[WIDTH-1+WIDTH*3:WIDTH*3] = x;
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3'd3 : ch_x[WIDTH-1+WIDTH*3:WIDTH*3] = x;
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3'd4 : ch_x[WIDTH-1+WIDTH*4:WIDTH*4] = x;
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3'd4 : ch_x[WIDTH-1+WIDTH*4:WIDTH*4] = x;
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3'd5 : ch_x[WIDTH-1+WIDTH*5:WIDTH*5] = x;
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3'd5 : ch_x[WIDTH-1+WIDTH*5:WIDTH*5] = x;
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3'd6 : ch_x[WIDTH-1+WIDTH*6:WIDTH*6] = x;
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3'd6 : ch_x[WIDTH-1+WIDTH*6:WIDTH*6] = x;
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3'd7 : ch_x[WIDTH-1+WIDTH*7:WIDTH*7] = x;
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3'd7 : ch_x[WIDTH-1+WIDTH*7:WIDTH*7] = x;
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default :
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default :
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ch_x[WIDTH-1:0] = x;
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ch_x[WIDTH-1:0] = x;
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endcase
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endcase
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end
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end
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endmodule
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endmodule
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