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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Author: Eyal Hochberg ////
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//// eyal@provartec.com ////
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//// ////
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//// Downloaded from: http://www.opencores.org ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2010 Provartec LTD ////
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//// www.provartec.com ////
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//// info@provartec.com ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation.////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more////
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//// details. http://www.gnu.org/licenses/lgpl.html ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//---------------------------------------------------------
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//---------------------------------------------------------
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//-- File generated by RobustVerilog parser
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//-- File generated by RobustVerilog parser
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//-- Version: 1.0
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//-- Version: 1.0
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//-- Invoked Fri Mar 25 23:36:57 2011
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//-- Invoked Fri Mar 25 23:36:57 2011
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//--
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//--
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//-- Source file: prgen_swap64.v
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//-- Source file: prgen_swap64.v
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//---------------------------------------------------------
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//---------------------------------------------------------
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module prgen_swap64 (end_swap,data_in,data_out,bsel_in,bsel_out);
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module prgen_swap64 (end_swap,data_in,data_out,bsel_in,bsel_out);
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input [1:0] end_swap;
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input [1:0] end_swap;
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input [63:0] data_in;
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input [63:0] data_in;
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output [63:0] data_out;
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output [63:0] data_out;
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input [7:0] bsel_in;
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input [7:0] bsel_in;
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output [7:0] bsel_out;
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output [7:0] bsel_out;
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wire [31:0] data_in_low;
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wire [31:0] data_in_low;
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wire [31:0] data_in_high;
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wire [31:0] data_in_high;
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wire [31:0] data_out_low;
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wire [31:0] data_out_low;
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wire [31:0] data_out_high;
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wire [31:0] data_out_high;
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wire [3:0] bsel_in_low;
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wire [3:0] bsel_in_low;
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wire [3:0] bsel_in_high;
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wire [3:0] bsel_in_high;
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wire [3:0] bsel_out_low;
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wire [3:0] bsel_out_low;
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wire [3:0] bsel_out_high;
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wire [3:0] bsel_out_high;
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assign data_in_low = end_swap == 2'b11 ? data_in[63:32] : data_in[31:0];
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assign data_in_low = end_swap == 2'b11 ? data_in[63:32] : data_in[31:0];
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assign data_in_high = end_swap == 2'b11 ? data_in[31:0] : data_in[63:32];
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assign data_in_high = end_swap == 2'b11 ? data_in[31:0] : data_in[63:32];
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assign bsel_in_low = end_swap == 2'b11 ? bsel_in[7:4] : bsel_in[3:0];
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assign bsel_in_low = end_swap == 2'b11 ? bsel_in[7:4] : bsel_in[3:0];
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assign bsel_in_high = end_swap == 2'b11 ? bsel_in[3:0] : bsel_in[7:4];
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assign bsel_in_high = end_swap == 2'b11 ? bsel_in[3:0] : bsel_in[7:4];
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prgen_swap32 swap32_low(
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prgen_swap32 swap32_low(
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.end_swap(end_swap),
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.end_swap(end_swap),
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.data_in(data_in_low),
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.data_in(data_in_low),
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.data_out(data_out_low),
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.data_out(data_out_low),
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.bsel_in(bsel_in_low),
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.bsel_in(bsel_in_low),
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.bsel_out(bsel_out_low)
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.bsel_out(bsel_out_low)
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);
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);
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prgen_swap32 swap32_high(
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prgen_swap32 swap32_high(
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.end_swap(end_swap),
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.end_swap(end_swap),
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.data_in(data_in_high),
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.data_in(data_in_high),
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.data_out(data_out_high),
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.data_out(data_out_high),
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.bsel_in(bsel_in_high),
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.bsel_in(bsel_in_high),
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.bsel_out(bsel_out_high)
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.bsel_out(bsel_out_high)
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);
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);
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assign data_out = {data_out_high, data_out_low};
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assign data_out = {data_out_high, data_out_low};
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assign bsel_out = {bsel_out_high, bsel_out_low};
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assign bsel_out = {bsel_out_high, bsel_out_low};
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endmodule
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endmodule
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