dmx/ 0000755 0001750 0001750 00000000000 11431235221 012024 5 ustar lekernel lekernel dmx/rtl/ 0000755 0001750 0001750 00000000000 11431045124 012626 5 ustar lekernel lekernel dmx/rtl/dmx_tx.v 0000644 0001750 0001750 00000015026 11431045124 014324 0 ustar lekernel lekernel /*
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dmx/ 0000755 0001750 0001750 00000000000 11431235221 012024 5 ustar lekernel lekernel dmx/rtl/ 0000755 0001750 0001750 00000000000 11431045124 012626 5 ustar lekernel lekernel dmx/rtl/dmx_tx.v 0000644 0001750 0001750 00000015026 11431045124 014324 0 ustar lekernel lekernel /*
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* Milkymist VJ SoC
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* Milkymist VJ SoC
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* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
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* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
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*
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*
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* This program is free software: you can redistribute it and/or modify
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, version 3 of the License.
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* the Free Software Foundation, version 3 of the License.
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*
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*
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* This program is distributed in the hope that it will be useful,
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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* GNU General Public License for more details.
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*
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*
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* You should have received a copy of the GNU General Public License
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see .
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* along with this program. If not, see .
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*/
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*/
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|
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module dmx_tx #(
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module dmx_tx #(
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parameter csr_addr = 4'h0,
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parameter csr_addr = 4'h0,
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parameter clk_freq = 100000000
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parameter clk_freq = 100000000
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) (
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) (
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input sys_clk,
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input sys_clk,
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input sys_rst,
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input sys_rst,
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|
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input [13:0] csr_a,
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input [13:0] csr_a,
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input csr_we,
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input csr_we,
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input [31:0] csr_di,
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input [31:0] csr_di,
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output [31:0] csr_do,
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output [31:0] csr_do,
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|
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input thru,
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input thru,
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output tx
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output tx
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);
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);
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|
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/* RAM and CSR interface */
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/* RAM and CSR interface */
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|
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wire csr_selected = csr_a[13:10] == csr_addr;
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wire csr_selected = csr_a[13:10] == csr_addr;
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|
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wire csr_channels_we;
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wire csr_channels_we;
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wire [31:0] csr_do_channels;
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wire [31:0] csr_do_channels;
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wire [8:0] channel_a;
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wire [8:0] channel_a;
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wire [7:0] channel_d;
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wire [7:0] channel_d;
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dmx_dpram channels(
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dmx_dpram channels(
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.clk(sys_clk),
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.clk(sys_clk),
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|
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.a(csr_a[8:0]),
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.a(csr_a[8:0]),
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.we(csr_channels_we),
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.we(csr_channels_we),
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.di(csr_di[7:0]),
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.di(csr_di[7:0]),
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.do(csr_do_channels[7:0]),
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.do(csr_do_channels[7:0]),
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|
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.a2(channel_a),
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.a2(channel_a),
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.we2(1'b0),
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.we2(1'b0),
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.di2(8'hxx),
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.di2(8'hxx),
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.do2(channel_d)
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.do2(channel_d)
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);
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);
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assign csr_channels_we = csr_selected & ~csr_a[9] & csr_we;
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assign csr_channels_we = csr_selected & ~csr_a[9] & csr_we;
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assign csr_do_channels[31:8] = 24'h000000;
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assign csr_do_channels[31:8] = 24'h000000;
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|
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reg thru_en;
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reg thru_en;
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|
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reg [31:0] csr_do_reg;
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reg [31:0] csr_do_reg;
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reg csr_do_sel;
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reg csr_do_sel;
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always @(posedge sys_clk) begin
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always @(posedge sys_clk) begin
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if(sys_rst) begin
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if(sys_rst) begin
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csr_do_reg <= 32'd0;
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csr_do_reg <= 32'd0;
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csr_do_sel <= 1'b0;
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csr_do_sel <= 1'b0;
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thru_en <= 1'b0;
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thru_en <= 1'b0;
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end else begin
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end else begin
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csr_do_reg <= 32'd0;
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csr_do_reg <= 32'd0;
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csr_do_sel <= 1'b0;
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csr_do_sel <= 1'b0;
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if(csr_selected) begin
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if(csr_selected) begin
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csr_do_sel <= ~csr_a[9];
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csr_do_sel <= ~csr_a[9];
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csr_do_reg <= thru_en;
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csr_do_reg <= thru_en;
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if(csr_we) begin
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if(csr_we) begin
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if(csr_a[9])
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if(csr_a[9])
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thru_en <= csr_di[0];
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thru_en <= csr_di[0];
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end
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end
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end
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end
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end
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end
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end
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end
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|
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assign csr_do = csr_do_sel ? csr_do_channels : csr_do_reg;
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assign csr_do = csr_do_sel ? csr_do_channels : csr_do_reg;
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|
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reg tx_gen;
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reg tx_gen;
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assign tx = thru_en ? thru : tx_gen;
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assign tx = thru_en ? thru : tx_gen;
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|
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/* Signal generator */
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/* Signal generator */
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|
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parameter divisor = clk_freq/250000;
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parameter divisor = clk_freq/250000;
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|
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reg ce;
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reg ce;
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reg [8:0] ce_counter;
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reg [8:0] ce_counter;
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always @(posedge sys_clk) begin
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always @(posedge sys_clk) begin
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if(sys_rst) begin
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if(sys_rst) begin
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ce <= 1'b0;
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ce <= 1'b0;
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ce_counter <= divisor-1;
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ce_counter <= divisor-1;
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end else begin
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end else begin
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if(ce_counter == 9'd0) begin
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if(ce_counter == 9'd0) begin
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ce <= 1'b1;
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ce <= 1'b1;
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ce_counter <= divisor-1;
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ce_counter <= divisor-1;
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end else begin
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end else begin
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ce <= 1'b0;
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ce <= 1'b0;
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ce_counter <= ce_counter - 9'd1;
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ce_counter <= ce_counter - 9'd1;
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end
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end
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end
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end
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end
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end
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reg [7:0] channel_d_r;
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reg [7:0] channel_d_r;
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reg channel_d_ce;
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reg channel_d_ce;
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always @(posedge sys_clk) begin
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always @(posedge sys_clk) begin
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if(channel_d_ce)
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if(channel_d_ce)
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channel_d_r <= channel_d;
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channel_d_r <= channel_d;
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end
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end
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reg [3:0] tx_sel;
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reg [3:0] tx_sel;
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parameter TX_SEL_B0 = 4'd0;
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parameter TX_SEL_B0 = 4'd0;
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parameter TX_SEL_B1 = 4'd1;
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parameter TX_SEL_B1 = 4'd1;
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parameter TX_SEL_B2 = 4'd2;
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parameter TX_SEL_B2 = 4'd2;
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parameter TX_SEL_B3 = 4'd3;
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parameter TX_SEL_B3 = 4'd3;
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parameter TX_SEL_B4 = 4'd4;
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parameter TX_SEL_B4 = 4'd4;
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parameter TX_SEL_B5 = 4'd5;
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parameter TX_SEL_B5 = 4'd5;
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parameter TX_SEL_B6 = 4'd6;
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parameter TX_SEL_B6 = 4'd6;
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parameter TX_SEL_B7 = 4'd7;
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parameter TX_SEL_B7 = 4'd7;
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parameter TX_SEL_HI = 4'd8;
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parameter TX_SEL_HI = 4'd8;
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parameter TX_SEL_LO = 4'd9;
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parameter TX_SEL_LO = 4'd9;
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|
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always @(posedge sys_clk) begin
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always @(posedge sys_clk) begin
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case(tx_sel)
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case(tx_sel)
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TX_SEL_B0: tx_gen <= channel_d_r[0];
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TX_SEL_B0: tx_gen <= channel_d_r[0];
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TX_SEL_B1: tx_gen <= channel_d_r[1];
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TX_SEL_B1: tx_gen <= channel_d_r[1];
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TX_SEL_B2: tx_gen <= channel_d_r[2];
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TX_SEL_B2: tx_gen <= channel_d_r[2];
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TX_SEL_B3: tx_gen <= channel_d_r[3];
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TX_SEL_B3: tx_gen <= channel_d_r[3];
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TX_SEL_B4: tx_gen <= channel_d_r[4];
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TX_SEL_B4: tx_gen <= channel_d_r[4];
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TX_SEL_B5: tx_gen <= channel_d_r[5];
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TX_SEL_B5: tx_gen <= channel_d_r[5];
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TX_SEL_B6: tx_gen <= channel_d_r[6];
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TX_SEL_B6: tx_gen <= channel_d_r[6];
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TX_SEL_B7: tx_gen <= channel_d_r[7];
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TX_SEL_B7: tx_gen <= channel_d_r[7];
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TX_SEL_HI: tx_gen <= 1'b1;
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TX_SEL_HI: tx_gen <= 1'b1;
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TX_SEL_LO: tx_gen <= 1'b0;
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TX_SEL_LO: tx_gen <= 1'b0;
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default: tx_gen <= 1'bx;
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default: tx_gen <= 1'bx;
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endcase
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endcase
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end
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end
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|
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reg acounter_reset;
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reg acounter_reset;
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reg acounter_ce;
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reg acounter_ce;
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reg frame_done;
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reg frame_done;
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reg [8:0] acounter;
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reg [8:0] acounter;
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always @(posedge sys_clk) begin
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always @(posedge sys_clk) begin
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if(ce) begin
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if(ce) begin
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if(acounter_reset) begin
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if(acounter_reset) begin
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acounter <= 9'd0;
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acounter <= 9'd0;
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frame_done <= 1'b0;
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frame_done <= 1'b0;
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end else if(acounter_ce) begin
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end else if(acounter_ce) begin
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acounter <= acounter + 9'd1;
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acounter <= acounter + 9'd1;
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frame_done <= acounter == 9'd511;
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frame_done <= acounter == 9'd511;
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end
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end
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end
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end
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end
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end
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assign channel_a = acounter;
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assign channel_a = acounter;
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|
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reg break_counter_reset;
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reg break_counter_reset;
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reg [4:0] break_counter;
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reg [4:0] break_counter;
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reg break_done;
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reg break_done;
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always @(posedge sys_clk) begin
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always @(posedge sys_clk) begin
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if(ce) begin
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if(ce) begin
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if(break_counter_reset) begin
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if(break_counter_reset) begin
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break_counter <= 5'd0;
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break_counter <= 5'd0;
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break_done <= 1'b0;
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break_done <= 1'b0;
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end else begin
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end else begin
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if(break_counter == 5'd25)
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if(break_counter == 5'd25)
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break_done <= 1'b1;
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break_done <= 1'b1;
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else
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else
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break_counter <= break_counter + 5'd1;
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break_counter <= break_counter + 5'd1;
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end
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end
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end
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end
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end
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end
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|
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reg [4:0] state;
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reg [4:0] state;
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reg [4:0] next_state;
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reg [4:0] next_state;
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|
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parameter MTBP = 5'd0;
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parameter MTBP = 5'd0;
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parameter BREAK = 5'd1;
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parameter BREAK = 5'd1;
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parameter MAB1 = 5'd2;
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parameter MAB1 = 5'd2;
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parameter MAB2 = 5'd3;
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parameter MAB2 = 5'd3;
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parameter SC_START = 5'd4;
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parameter SC_START = 5'd4;
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parameter SC_D0 = 5'd5;
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parameter SC_D0 = 5'd5;
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parameter SC_D1 = 5'd6;
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parameter SC_D1 = 5'd6;
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parameter SC_D2 = 5'd7;
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parameter SC_D2 = 5'd7;
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parameter SC_D3 = 5'd8;
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parameter SC_D3 = 5'd8;
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parameter SC_D4 = 5'd9;
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parameter SC_D4 = 5'd9;
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parameter SC_D5 = 5'd10;
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parameter SC_D5 = 5'd10;
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parameter SC_D6 = 5'd11;
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parameter SC_D6 = 5'd11;
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parameter SC_D7 = 5'd12;
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parameter SC_D7 = 5'd12;
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parameter SC_STOP1 = 5'd13;
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parameter SC_STOP1 = 5'd13;
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parameter SC_STOP2 = 5'd14;
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parameter SC_STOP2 = 5'd14;
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parameter START = 5'd15;
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parameter START = 5'd15;
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parameter D0 = 5'd16;
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parameter D0 = 5'd16;
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parameter D1 = 5'd17;
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parameter D1 = 5'd17;
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parameter D2 = 5'd18;
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parameter D2 = 5'd18;
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parameter D3 = 5'd19;
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parameter D3 = 5'd19;
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parameter D4 = 5'd20;
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parameter D4 = 5'd20;
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parameter D5 = 5'd21;
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parameter D5 = 5'd21;
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parameter D6 = 5'd22;
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parameter D6 = 5'd22;
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parameter D7 = 5'd23;
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parameter D7 = 5'd23;
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parameter STOP1 = 5'd24;
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parameter STOP1 = 5'd24;
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parameter STOP2 = 5'd25;
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parameter STOP2 = 5'd25;
|
|
|
always @(posedge sys_clk) begin
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always @(posedge sys_clk) begin
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if(sys_rst)
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if(sys_rst)
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state <= MTBP;
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state <= MTBP;
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else if(ce)
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else if(ce)
|
state <= next_state;
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state <= next_state;
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end
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end
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|
|
always @(*) begin
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always @(*) begin
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tx_sel = TX_SEL_HI;
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tx_sel = TX_SEL_HI;
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acounter_reset = 1'b1;
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acounter_reset = 1'b1;
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acounter_ce = 1'b0;
|
acounter_ce = 1'b0;
|
break_counter_reset = 1'b1;
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break_counter_reset = 1'b1;
|
|
|
channel_d_ce = 1'b0;
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channel_d_ce = 1'b0;
|
|
|
next_state = state;
|
next_state = state;
|
|
|
case(state)
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case(state)
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MTBP: next_state = BREAK;
|
MTBP: next_state = BREAK;
|
|
|
BREAK: begin
|
BREAK: begin
|
tx_sel = TX_SEL_LO;
|
tx_sel = TX_SEL_LO;
|
break_counter_reset = 1'b0;
|
break_counter_reset = 1'b0;
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if(break_done)
|
if(break_done)
|
next_state = MAB1;
|
next_state = MAB1;
|
end
|
end
|
|
|
MAB1: next_state = MAB2;
|
MAB1: next_state = MAB2;
|
MAB2: next_state = SC_START;
|
MAB2: next_state = SC_START;
|
|
|
SC_START: begin
|
SC_START: begin
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tx_sel = TX_SEL_LO;
|
tx_sel = TX_SEL_LO;
|
next_state = SC_D0;
|
next_state = SC_D0;
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end
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end
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SC_D0: begin
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SC_D0: begin
|
tx_sel = TX_SEL_LO;
|
tx_sel = TX_SEL_LO;
|
next_state = SC_D1;
|
next_state = SC_D1;
|
end
|
end
|
SC_D1: begin
|
SC_D1: begin
|
tx_sel = TX_SEL_LO;
|
tx_sel = TX_SEL_LO;
|
next_state = SC_D2;
|
next_state = SC_D2;
|
end
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end
|
SC_D2: begin
|
SC_D2: begin
|
tx_sel = TX_SEL_LO;
|
tx_sel = TX_SEL_LO;
|
next_state = SC_D3;
|
next_state = SC_D3;
|
end
|
end
|
SC_D3: begin
|
SC_D3: begin
|
tx_sel = TX_SEL_LO;
|
tx_sel = TX_SEL_LO;
|
next_state = SC_D4;
|
next_state = SC_D4;
|
end
|
end
|
SC_D4: begin
|
SC_D4: begin
|
tx_sel = TX_SEL_LO;
|
tx_sel = TX_SEL_LO;
|
next_state = SC_D5;
|
next_state = SC_D5;
|
end
|
end
|
SC_D5: begin
|
SC_D5: begin
|
tx_sel = TX_SEL_LO;
|
tx_sel = TX_SEL_LO;
|
next_state = SC_D6;
|
next_state = SC_D6;
|
end
|
end
|
SC_D6: begin
|
SC_D6: begin
|
tx_sel = TX_SEL_LO;
|
tx_sel = TX_SEL_LO;
|
next_state = SC_D7;
|
next_state = SC_D7;
|
end
|
end
|
SC_D7: begin
|
SC_D7: begin
|
tx_sel = TX_SEL_LO;
|
tx_sel = TX_SEL_LO;
|
next_state = SC_STOP1;
|
next_state = SC_STOP1;
|
end
|
end
|
SC_STOP1: next_state = SC_STOP2;
|
SC_STOP1: next_state = SC_STOP2;
|
SC_STOP2: next_state = START;
|
SC_STOP2: next_state = START;
|
|
|
START: begin
|
START: begin
|
tx_sel = TX_SEL_LO;
|
tx_sel = TX_SEL_LO;
|
acounter_reset = 1'b0;
|
acounter_reset = 1'b0;
|
channel_d_ce = 1'b1;
|
channel_d_ce = 1'b1;
|
next_state = D0;
|
next_state = D0;
|
end
|
end
|
D0: begin
|
D0: begin
|
tx_sel = TX_SEL_B0;
|
tx_sel = TX_SEL_B0;
|
acounter_reset = 1'b0;
|
acounter_reset = 1'b0;
|
next_state = D1;
|
next_state = D1;
|
end
|
end
|
D1: begin
|
D1: begin
|
tx_sel = TX_SEL_B1;
|
tx_sel = TX_SEL_B1;
|
acounter_reset = 1'b0;
|
acounter_reset = 1'b0;
|
next_state = D2;
|
next_state = D2;
|
end
|
end
|
D2: begin
|
D2: begin
|
tx_sel = TX_SEL_B2;
|
tx_sel = TX_SEL_B2;
|
acounter_reset = 1'b0;
|
acounter_reset = 1'b0;
|
next_state = D3;
|
next_state = D3;
|
end
|
end
|
D3: begin
|
D3: begin
|
tx_sel = TX_SEL_B3;
|
tx_sel = TX_SEL_B3;
|
acounter_reset = 1'b0;
|
acounter_reset = 1'b0;
|
next_state = D4;
|
next_state = D4;
|
end
|
end
|
D4: begin
|
D4: begin
|
tx_sel = TX_SEL_B4;
|
tx_sel = TX_SEL_B4;
|
acounter_reset = 1'b0;
|
acounter_reset = 1'b0;
|
next_state = D5;
|
next_state = D5;
|
end
|
end
|
D5: begin
|
D5: begin
|
tx_sel = TX_SEL_B5;
|
tx_sel = TX_SEL_B5;
|
acounter_reset = 1'b0;
|
acounter_reset = 1'b0;
|
next_state = D6;
|
next_state = D6;
|
end
|
end
|
D6: begin
|
D6: begin
|
tx_sel = TX_SEL_B6;
|
tx_sel = TX_SEL_B6;
|
acounter_reset = 1'b0;
|
acounter_reset = 1'b0;
|
next_state = D7;
|
next_state = D7;
|
end
|
end
|
D7: begin
|
D7: begin
|
tx_sel = TX_SEL_B7;
|
tx_sel = TX_SEL_B7;
|
acounter_reset = 1'b0;
|
acounter_reset = 1'b0;
|
next_state = STOP1;
|
next_state = STOP1;
|
end
|
end
|
STOP1: begin
|
STOP1: begin
|
acounter_reset = 1'b0;
|
acounter_reset = 1'b0;
|
acounter_ce = 1'b1;
|
acounter_ce = 1'b1;
|
next_state = STOP2;
|
next_state = STOP2;
|
end
|
end
|
STOP2: begin
|
STOP2: begin
|
acounter_reset = 1'b0;
|
acounter_reset = 1'b0;
|
if(frame_done)
|
if(frame_done)
|
next_state = MTBP;
|
next_state = MTBP;
|
else
|
else
|
next_state = START;
|
next_state = START;
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
|
|
endmodule
|
endmodule
|
dmx/rtl/dmx_dpram.v 0000644 0001750 0001750 00000002432 11431045124 014771 0 ustar lekernel lekernel /*
|
dmx/rtl/dmx_dpram.v 0000644 0001750 0001750 00000002432 11431045124 014771 0 ustar lekernel lekernel /*
|
* Milkymist VJ SoC
|
* Milkymist VJ SoC
|
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
|
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
|
*
|
*
|
* This program is free software: you can redistribute it and/or modify
|
* This program is free software: you can redistribute it and/or modify
|
* it under the terms of the GNU General Public License as published by
|
* it under the terms of the GNU General Public License as published by
|
* the Free Software Foundation, version 3 of the License.
|
* the Free Software Foundation, version 3 of the License.
|
*
|
*
|
* This program is distributed in the hope that it will be useful,
|
* This program is distributed in the hope that it will be useful,
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
* GNU General Public License for more details.
|
* GNU General Public License for more details.
|
*
|
*
|
* You should have received a copy of the GNU General Public License
|
* You should have received a copy of the GNU General Public License
|
* along with this program. If not, see .
|
* along with this program. If not, see .
|
*/
|
*/
|
|
|
module dmx_dpram #(
|
module dmx_dpram #(
|
parameter depth = 9,
|
parameter depth = 9,
|
parameter width = 8
|
parameter width = 8
|
) (
|
) (
|
input clk,
|
input clk,
|
|
|
input [depth-1:0] a,
|
input [depth-1:0] a,
|
input we,
|
input we,
|
input [width-1:0] di,
|
input [width-1:0] di,
|
output reg [width-1:0] do,
|
output reg [width-1:0] do,
|
|
|
input [depth-1:0] a2,
|
input [depth-1:0] a2,
|
input we2,
|
input we2,
|
input [width-1:0] di2,
|
input [width-1:0] di2,
|
output reg [width-1:0] do2
|
output reg [width-1:0] do2
|
);
|
);
|
|
|
reg [width-1:0] ram[0:(1 << depth)-1];
|
reg [width-1:0] ram[0:(1 << depth)-1];
|
|
|
always @(posedge clk) begin
|
always @(posedge clk) begin
|
if(we)
|
if(we)
|
ram[a] <= di;
|
ram[a] <= di;
|
do <= ram[a];
|
do <= ram[a];
|
if(we2)
|
if(we2)
|
ram[a2] <= di2;
|
ram[a2] <= di2;
|
do2 <= ram[a2];
|
do2 <= ram[a2];
|
end
|
end
|
|
|
// synthesis translate_off
|
// synthesis translate_off
|
integer i;
|
integer i;
|
initial begin
|
initial begin
|
for(i=0;i<(1 << depth);i=i+1)
|
for(i=0;i<(1 << depth);i=i+1)
|
ram[i] = {width{1'b0}};
|
ram[i] = {width{1'b0}};
|
ram[0] = 8'h55;
|
ram[0] = 8'h55;
|
ram[1] = 8'haa;
|
ram[1] = 8'haa;
|
ram[511] = 8'hff;
|
ram[511] = 8'hff;
|
end
|
end
|
// synthesis translate_on
|
// synthesis translate_on
|
|
|
endmodule
|
endmodule
|
dmx/rtl/dmx_rx.v 0000644 0001750 0001750 00000012276 11431045124 014326 0 ustar lekernel lekernel /*
|
dmx/rtl/dmx_rx.v 0000644 0001750 0001750 00000012276 11431045124 014326 0 ustar lekernel lekernel /*
|
* Milkymist VJ SoC
|
* Milkymist VJ SoC
|
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
|
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
|
*
|
*
|
* This program is free software: you can redistribute it and/or modify
|
* This program is free software: you can redistribute it and/or modify
|
* it under the terms of the GNU General Public License as published by
|
* it under the terms of the GNU General Public License as published by
|
* the Free Software Foundation, version 3 of the License.
|
* the Free Software Foundation, version 3 of the License.
|
*
|
*
|
* This program is distributed in the hope that it will be useful,
|
* This program is distributed in the hope that it will be useful,
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
* GNU General Public License for more details.
|
* GNU General Public License for more details.
|
*
|
*
|
* You should have received a copy of the GNU General Public License
|
* You should have received a copy of the GNU General Public License
|
* along with this program. If not, see .
|
* along with this program. If not, see .
|
*/
|
*/
|
|
|
module dmx_rx #(
|
module dmx_rx #(
|
parameter csr_addr = 4'h0,
|
parameter csr_addr = 4'h0,
|
parameter clk_freq = 100000000
|
parameter clk_freq = 100000000
|
) (
|
) (
|
input sys_clk,
|
input sys_clk,
|
input sys_rst,
|
input sys_rst,
|
|
|
input [13:0] csr_a,
|
input [13:0] csr_a,
|
input csr_we,
|
input csr_we,
|
input [31:0] csr_di,
|
input [31:0] csr_di,
|
output [31:0] csr_do,
|
output [31:0] csr_do,
|
|
|
input rx
|
input rx
|
);
|
);
|
|
|
/* RAM and CSR interface */
|
/* RAM and CSR interface */
|
|
|
wire csr_selected = csr_a[13:10] == csr_addr;
|
wire csr_selected = csr_a[13:10] == csr_addr;
|
|
|
wire [7:0] csr_channel;
|
wire [7:0] csr_channel;
|
reg [8:0] channel_a;
|
reg [8:0] channel_a;
|
reg channel_we;
|
reg channel_we;
|
reg [7:0] channel_d;
|
reg [7:0] channel_d;
|
dmx_dpram channels(
|
dmx_dpram channels(
|
.clk(sys_clk),
|
.clk(sys_clk),
|
|
|
.a(csr_a[8:0]),
|
.a(csr_a[8:0]),
|
.we(1'b0),
|
.we(1'b0),
|
.di(8'hxx),
|
.di(8'hxx),
|
.do(csr_channel),
|
.do(csr_channel),
|
|
|
.a2(channel_a),
|
.a2(channel_a),
|
.we2(channel_we),
|
.we2(channel_we),
|
.di2(channel_d),
|
.di2(channel_d),
|
.do2()
|
.do2()
|
);
|
);
|
|
|
always @(posedge sys_clk) begin
|
always @(posedge sys_clk) begin
|
if(channel_we)
|
if(channel_we)
|
$display("Received value %x for channel %x", channel_d, channel_a);
|
$display("Received value %x for channel %x", channel_d, channel_a);
|
end
|
end
|
|
|
reg csr_selected_r;
|
reg csr_selected_r;
|
always @(posedge sys_clk)
|
always @(posedge sys_clk)
|
csr_selected_r <= csr_selected;
|
csr_selected_r <= csr_selected;
|
|
|
assign csr_do = {24'h000000, csr_selected_r ? csr_channel : 8'h00};
|
assign csr_do = {24'h000000, csr_selected_r ? csr_channel : 8'h00};
|
|
|
/* Synchronizer */
|
/* Synchronizer */
|
|
|
reg rx_r0;
|
reg rx_r0;
|
reg rx_r;
|
reg rx_r;
|
always @(posedge sys_clk) begin
|
always @(posedge sys_clk) begin
|
rx_r0 <= rx;
|
rx_r0 <= rx;
|
rx_r <= rx_r0;
|
rx_r <= rx_r0;
|
end
|
end
|
|
|
/* Signal decoder */
|
/* Signal decoder */
|
|
|
parameter divisor = clk_freq/250000;
|
parameter divisor = clk_freq/250000;
|
parameter halfbit = clk_freq/500000;
|
parameter halfbit = clk_freq/500000;
|
|
|
reg ce_load;
|
reg ce_load;
|
reg ce;
|
reg ce;
|
reg [8:0] ce_counter;
|
reg [8:0] ce_counter;
|
always @(posedge sys_clk) begin
|
always @(posedge sys_clk) begin
|
if(ce_load) begin
|
if(ce_load) begin
|
ce <= 1'b0;
|
ce <= 1'b0;
|
ce_counter <= halfbit-1;
|
ce_counter <= halfbit-1;
|
end else begin
|
end else begin
|
if(ce_counter == 9'd0) begin
|
if(ce_counter == 9'd0) begin
|
ce <= 1'b1;
|
ce <= 1'b1;
|
ce_counter <= divisor-1;
|
ce_counter <= divisor-1;
|
end else begin
|
end else begin
|
ce <= 1'b0;
|
ce <= 1'b0;
|
ce_counter <= ce_counter - 9'd1;
|
ce_counter <= ce_counter - 9'd1;
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
reg channel_a_reset;
|
reg channel_a_reset;
|
reg channel_a_ce;
|
reg channel_a_ce;
|
always @(posedge sys_clk) begin
|
always @(posedge sys_clk) begin
|
if(channel_a_reset)
|
if(channel_a_reset)
|
channel_a <= 9'd0;
|
channel_a <= 9'd0;
|
else if(channel_a_ce)
|
else if(channel_a_ce)
|
channel_a <= channel_a + 9'd1;
|
channel_a <= channel_a + 9'd1;
|
end
|
end
|
|
|
reg channel_d_load_en;
|
reg channel_d_load_en;
|
reg [2:0] channel_d_load;
|
reg [2:0] channel_d_load;
|
always @(posedge sys_clk) begin
|
always @(posedge sys_clk) begin
|
if(channel_d_load_en)
|
if(channel_d_load_en)
|
channel_d[channel_d_load] <= rx_r;
|
channel_d[channel_d_load] <= rx_r;
|
end
|
end
|
|
|
parameter break_threshold = clk_freq/11364;
|
parameter break_threshold = clk_freq/11364;
|
reg [12:0] break_counter;
|
reg [12:0] break_counter;
|
wire break = break_counter == 13'd0;
|
wire break = break_counter == 13'd0;
|
always @(posedge sys_clk) begin
|
always @(posedge sys_clk) begin
|
if(sys_rst|rx_r)
|
if(sys_rst|rx_r)
|
break_counter <= break_threshold;
|
break_counter <= break_threshold;
|
else if(~break)
|
else if(~break)
|
break_counter <= break_counter - 13'd1;
|
break_counter <= break_counter - 13'd1;
|
end
|
end
|
|
|
reg [3:0] state;
|
reg [3:0] state;
|
reg [3:0] next_state;
|
reg [3:0] next_state;
|
|
|
parameter WAIT_BREAK = 4'd0;
|
parameter WAIT_BREAK = 4'd0;
|
parameter WAIT_MAB = 4'd1;
|
parameter WAIT_MAB = 4'd1;
|
parameter WAIT_START = 4'd2;
|
parameter WAIT_START = 4'd2;
|
parameter SAMPLE_START = 4'd3;
|
parameter SAMPLE_START = 4'd3;
|
parameter SAMPLE0 = 4'd4;
|
parameter SAMPLE0 = 4'd4;
|
parameter SAMPLE1 = 4'd5;
|
parameter SAMPLE1 = 4'd5;
|
parameter SAMPLE2 = 4'd6;
|
parameter SAMPLE2 = 4'd6;
|
parameter SAMPLE3 = 4'd7;
|
parameter SAMPLE3 = 4'd7;
|
parameter SAMPLE4 = 4'd8;
|
parameter SAMPLE4 = 4'd8;
|
parameter SAMPLE5 = 4'd9;
|
parameter SAMPLE5 = 4'd9;
|
parameter SAMPLE6 = 4'd10;
|
parameter SAMPLE6 = 4'd10;
|
parameter SAMPLE7 = 4'd11;
|
parameter SAMPLE7 = 4'd11;
|
parameter SAMPLE_STOP1 = 4'd12;
|
parameter SAMPLE_STOP1 = 4'd12;
|
parameter SAMPLE_STOP2 = 4'd13;
|
parameter SAMPLE_STOP2 = 4'd13;
|
|
|
always @(posedge sys_clk) begin
|
always @(posedge sys_clk) begin
|
if(sys_rst)
|
if(sys_rst)
|
state <= WAIT_BREAK;
|
state <= WAIT_BREAK;
|
else
|
else
|
state <= next_state;
|
state <= next_state;
|
end
|
end
|
|
|
/* skip 1st byte (start code) */
|
/* skip 1st byte (start code) */
|
reg skip;
|
reg skip;
|
reg next_skip;
|
reg next_skip;
|
always @(posedge sys_clk)
|
always @(posedge sys_clk)
|
skip <= next_skip;
|
skip <= next_skip;
|
|
|
always @(*) begin
|
always @(*) begin
|
ce_load = 1'b0;
|
ce_load = 1'b0;
|
channel_a_reset = 1'b0;
|
channel_a_reset = 1'b0;
|
channel_a_ce = 1'b0;
|
channel_a_ce = 1'b0;
|
channel_we = 1'b0;
|
channel_we = 1'b0;
|
channel_d_load_en = 1'b0;
|
channel_d_load_en = 1'b0;
|
channel_d_load = 3'bxxx;
|
channel_d_load = 3'bxxx;
|
|
|
next_state = state;
|
next_state = state;
|
next_skip = skip;
|
next_skip = skip;
|
|
|
case(state)
|
case(state)
|
WAIT_BREAK: begin
|
WAIT_BREAK: begin
|
ce_load = 1'b1;
|
ce_load = 1'b1;
|
channel_a_reset = 1'b1;
|
channel_a_reset = 1'b1;
|
next_skip = 1'b1;
|
next_skip = 1'b1;
|
if(break)
|
if(break)
|
next_state = WAIT_MAB;
|
next_state = WAIT_MAB;
|
end
|
end
|
WAIT_MAB: begin
|
WAIT_MAB: begin
|
ce_load = 1'b1;
|
ce_load = 1'b1;
|
channel_a_reset = 1'b1;
|
channel_a_reset = 1'b1;
|
if(rx_r)
|
if(rx_r)
|
next_state = WAIT_START;
|
next_state = WAIT_START;
|
end
|
end
|
|
|
WAIT_START: begin
|
WAIT_START: begin
|
ce_load = 1'b1;
|
ce_load = 1'b1;
|
if(~rx_r)
|
if(~rx_r)
|
next_state = SAMPLE_START;
|
next_state = SAMPLE_START;
|
end
|
end
|
SAMPLE_START: begin
|
SAMPLE_START: begin
|
if(ce) begin
|
if(ce) begin
|
if(rx_r) /* confirm start bit */
|
if(rx_r) /* confirm start bit */
|
next_state = WAIT_BREAK;
|
next_state = WAIT_BREAK;
|
else
|
else
|
next_state = SAMPLE0;
|
next_state = SAMPLE0;
|
end
|
end
|
end
|
end
|
SAMPLE0: begin
|
SAMPLE0: begin
|
channel_d_load_en = 1'b1;
|
channel_d_load_en = 1'b1;
|
channel_d_load = 3'd0;
|
channel_d_load = 3'd0;
|
if(ce)
|
if(ce)
|
next_state = SAMPLE1;
|
next_state = SAMPLE1;
|
end
|
end
|
SAMPLE1: begin
|
SAMPLE1: begin
|
channel_d_load_en = 1'b1;
|
channel_d_load_en = 1'b1;
|
channel_d_load = 3'd1;
|
channel_d_load = 3'd1;
|
if(ce)
|
if(ce)
|
next_state = SAMPLE2;
|
next_state = SAMPLE2;
|
end
|
end
|
SAMPLE2: begin
|
SAMPLE2: begin
|
channel_d_load_en = 1'b1;
|
channel_d_load_en = 1'b1;
|
channel_d_load = 3'd2;
|
channel_d_load = 3'd2;
|
if(ce)
|
if(ce)
|
next_state = SAMPLE3;
|
next_state = SAMPLE3;
|
end
|
end
|
SAMPLE3: begin
|
SAMPLE3: begin
|
channel_d_load_en = 1'b1;
|
channel_d_load_en = 1'b1;
|
channel_d_load = 3'd3;
|
channel_d_load = 3'd3;
|
if(ce)
|
if(ce)
|
next_state = SAMPLE4;
|
next_state = SAMPLE4;
|
end
|
end
|
SAMPLE4: begin
|
SAMPLE4: begin
|
channel_d_load_en = 1'b1;
|
channel_d_load_en = 1'b1;
|
channel_d_load = 3'd4;
|
channel_d_load = 3'd4;
|
if(ce)
|
if(ce)
|
next_state = SAMPLE5;
|
next_state = SAMPLE5;
|
end
|
end
|
SAMPLE5: begin
|
SAMPLE5: begin
|
channel_d_load_en = 1'b1;
|
channel_d_load_en = 1'b1;
|
channel_d_load = 3'd5;
|
channel_d_load = 3'd5;
|
if(ce)
|
if(ce)
|
next_state = SAMPLE6;
|
next_state = SAMPLE6;
|
end
|
end
|
SAMPLE6: begin
|
SAMPLE6: begin
|
channel_d_load_en = 1'b1;
|
channel_d_load_en = 1'b1;
|
channel_d_load = 3'd6;
|
channel_d_load = 3'd6;
|
if(ce)
|
if(ce)
|
next_state = SAMPLE7;
|
next_state = SAMPLE7;
|
end
|
end
|
SAMPLE7: begin
|
SAMPLE7: begin
|
channel_d_load_en = 1'b1;
|
channel_d_load_en = 1'b1;
|
channel_d_load = 3'd7;
|
channel_d_load = 3'd7;
|
if(ce)
|
if(ce)
|
next_state = SAMPLE_STOP1;
|
next_state = SAMPLE_STOP1;
|
end
|
end
|
SAMPLE_STOP1: begin
|
SAMPLE_STOP1: begin
|
if(ce) begin
|
if(ce) begin
|
if(rx_r) /* verify 1st stop bit */
|
if(rx_r) /* verify 1st stop bit */
|
next_state = SAMPLE_STOP2;
|
next_state = SAMPLE_STOP2;
|
else
|
else
|
next_state = WAIT_BREAK;
|
next_state = WAIT_BREAK;
|
end
|
end
|
end
|
end
|
SAMPLE_STOP2: begin
|
SAMPLE_STOP2: begin
|
if(ce) begin
|
if(ce) begin
|
if(rx_r) begin /* verify 2nd stop bit */
|
if(rx_r) begin /* verify 2nd stop bit */
|
next_skip = 1'b0;
|
next_skip = 1'b0;
|
if(~skip) begin
|
if(~skip) begin
|
channel_we = 1'b1;
|
channel_we = 1'b1;
|
channel_a_ce = 1'b1;
|
channel_a_ce = 1'b1;
|
end
|
end
|
next_state = WAIT_START;
|
next_state = WAIT_START;
|
end else
|
end else
|
next_state = WAIT_BREAK;
|
next_state = WAIT_BREAK;
|
end
|
end
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
|
|
endmodule
|
endmodule
|
dmx/test/ 0000755 0001750 0001750 00000000000 11431045124 013004 5 ustar lekernel lekernel dmx/test/tb_dmx.v 0000644 0001750 0001750 00000004070 11431045124 014451 0 ustar lekernel lekernel /*
|
dmx/test/ 0000755 0001750 0001750 00000000000 11431045124 013004 5 ustar lekernel lekernel dmx/test/tb_dmx.v 0000644 0001750 0001750 00000004070 11431045124 014451 0 ustar lekernel lekernel /*
|
* Milkymist VJ SoC
|
* Milkymist VJ SoC
|
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
|
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
|
*
|
*
|
* This program is free software: you can redistribute it and/or modify
|
* This program is free software: you can redistribute it and/or modify
|
* it under the terms of the GNU General Public License as published by
|
* it under the terms of the GNU General Public License as published by
|
* the Free Software Foundation, version 3 of the License.
|
* the Free Software Foundation, version 3 of the License.
|
*
|
*
|
* This program is distributed in the hope that it will be useful,
|
* This program is distributed in the hope that it will be useful,
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
* GNU General Public License for more details.
|
* GNU General Public License for more details.
|
*
|
*
|
* You should have received a copy of the GNU General Public License
|
* You should have received a copy of the GNU General Public License
|
* along with this program. If not, see .
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* along with this program. If not, see .
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*/
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*/
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|
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module tb_dmx();
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module tb_dmx();
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|
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reg sys_clk;
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reg sys_clk;
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reg sys_rst;
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reg sys_rst;
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|
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/* 83.333MHz system clock */
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/* 83.333MHz system clock */
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initial sys_clk = 1'b0;
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initial sys_clk = 1'b0;
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always #6 sys_clk = ~sys_clk;
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always #6 sys_clk = ~sys_clk;
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|
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reg [13:0] csr_a;
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reg [13:0] csr_a;
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reg csr_we;
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reg csr_we;
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reg [31:0] csr_di;
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reg [31:0] csr_di;
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wire [31:0] csr_do_tx;
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wire [31:0] csr_do_tx;
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wire [31:0] csr_do_rx;
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wire [31:0] csr_do_rx;
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|
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wire dmx_signal;
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wire dmx_signal;
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dmx_tx #(
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dmx_tx #(
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.csr_addr(4'h0),
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.csr_addr(4'h0),
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.clk_freq(83333333)
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.clk_freq(83333333)
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) tx_dut (
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) tx_dut (
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.sys_clk(sys_clk),
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.sys_clk(sys_clk),
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.sys_rst(sys_rst),
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.sys_rst(sys_rst),
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|
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.csr_a(csr_a),
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.csr_a(csr_a),
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.csr_we(csr_we),
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.csr_we(csr_we),
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.csr_do(csr_do_tx),
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.csr_do(csr_do_tx),
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.csr_di(csr_di),
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.csr_di(csr_di),
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|
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.thru(1'b0),
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.thru(1'b0),
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.tx(dmx_signal)
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.tx(dmx_signal)
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);
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);
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dmx_rx #(
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dmx_rx #(
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.csr_addr(4'h1),
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.csr_addr(4'h1),
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.clk_freq(83333333)
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.clk_freq(83333333)
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) rx_dut (
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) rx_dut (
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.sys_clk(sys_clk),
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.sys_clk(sys_clk),
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.sys_rst(sys_rst),
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.sys_rst(sys_rst),
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|
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.csr_a(csr_a),
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.csr_a(csr_a),
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.csr_we(csr_we),
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.csr_we(csr_we),
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.csr_do(csr_do_rx),
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.csr_do(csr_do_rx),
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.csr_di(csr_di),
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.csr_di(csr_di),
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|
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.rx(dmx_signal)
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.rx(dmx_signal)
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);
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);
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task waitclock;
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task waitclock;
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begin
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begin
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@(posedge sys_clk);
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@(posedge sys_clk);
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#1;
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#1;
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end
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end
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endtask
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endtask
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task csrwrite;
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task csrwrite;
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input [31:0] address;
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input [31:0] address;
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input [31:0] data;
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input [31:0] data;
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begin
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begin
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csr_a = address[16:2];
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csr_a = address[16:2];
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csr_di = data;
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csr_di = data;
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csr_we = 1'b1;
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csr_we = 1'b1;
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waitclock;
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waitclock;
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$display("CSR write: %x=%x", address, data);
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$display("CSR write: %x=%x", address, data);
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csr_we = 1'b0;
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csr_we = 1'b0;
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end
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end
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endtask
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endtask
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task csrread;
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task csrread;
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input [31:0] address;
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input [31:0] address;
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begin
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begin
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csr_a = address[16:2];
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csr_a = address[16:2];
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waitclock;
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waitclock;
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$display("CSR read : %x=%x", address, csr_do_tx|csr_do_rx);
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$display("CSR read : %x=%x", address, csr_do_tx|csr_do_rx);
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end
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end
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endtask
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endtask
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always begin
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always begin
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$dumpfile("dmx.vcd");
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$dumpfile("dmx.vcd");
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$dumpvars(0, tx_dut);
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$dumpvars(0, tx_dut);
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$dumpvars(0, rx_dut);
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$dumpvars(0, rx_dut);
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|
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/* Reset / Initialize our logic */
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/* Reset / Initialize our logic */
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sys_rst = 1'b1;
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sys_rst = 1'b1;
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|
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waitclock;
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waitclock;
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|
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sys_rst = 1'b0;
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sys_rst = 1'b0;
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waitclock;
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waitclock;
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csrread(32'h0000);
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csrread(32'h0000);
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csrwrite(32'h0000, 32'hff);
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csrwrite(32'h0000, 32'hff);
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csrread(32'h0000);
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csrread(32'h0000);
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#1000000;
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#1000000;
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csrread(32'h1000);
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csrread(32'h1000);
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csrread(32'h1004);
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csrread(32'h1004);
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#50000000;
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#50000000;
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$finish;
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$finish;
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end
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end
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endmodule
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endmodule
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dmx/test/Makefile 0000644 0001750 0001750 00000000177 11431045124 014451 0 ustar lekernel lekernel SOURCES=tb_dmx.v $(wildcard ../rtl/*.v)
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dmx/test/Makefile 0000644 0001750 0001750 00000000177 11431045124 014451 0 ustar lekernel lekernel SOURCES=tb_dmx.v $(wildcard ../rtl/*.v)
|
|
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all: sim
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all: sim
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|
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sim:
|
sim:
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cver $(SOURCES)
|
cver $(SOURCES)
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|
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clean:
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clean:
|
rm -f verilog.log dmx.vcd
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rm -f verilog.log dmx.vcd
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|
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.PHONY: clean sim
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.PHONY: clean sim
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dmx/doc/ 0000755 0001750 0001750 00000000000 11431240556 012600 5 ustar lekernel lekernel dmx/doc/dmx.tex 0000644 0001750 0001750 00000004264 11431240530 014110 0 ustar lekernel lekernel \documentclass[a4paper,11pt]{article}
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dmx/doc/ 0000755 0001750 0001750 00000000000 11431543453 012602 5 ustar lekernel lekernel dmx/doc/dmx.tex 0000644 0001750 0001750 00000004264 11431240530 014110 0 ustar lekernel lekernel \documentclass[a4paper,11pt]{article}
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\usepackage{fullpage}
|
\usepackage{fullpage}
|
\usepackage[latin1]{inputenc}
|
\usepackage[latin1]{inputenc}
|
\usepackage[T1]{fontenc}
|
\usepackage[T1]{fontenc}
|
\usepackage[normalem]{ulem}
|
\usepackage[normalem]{ulem}
|
\usepackage[english]{babel}
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\usepackage[english]{babel}
|
\usepackage{listings,babel}
|
\usepackage{listings,babel}
|
\lstset{breaklines=true,basicstyle=\ttfamily}
|
\lstset{breaklines=true,basicstyle=\ttfamily}
|
\usepackage{graphicx}
|
\usepackage{graphicx}
|
\usepackage{moreverb}
|
\usepackage{moreverb}
|
\usepackage{url}
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\usepackage{url}
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|
|
\title{DMX cores}
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\title{DMX cores}
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\author{S\'ebastien Bourdeauducq}
|
\author{S\'ebastien Bourdeauducq}
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\date{August 2010}
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\date{August 2010}
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\begin{document}
|
\begin{document}
|
\setlength{\parindent}{0pt}
|
\setlength{\parindent}{0pt}
|
\setlength{\parskip}{5pt}
|
\setlength{\parskip}{5pt}
|
\maketitle{}
|
\maketitle{}
|
\section{Overview}
|
\section{Overview}
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The DMX cores are made of a transmitter and receiver cores. Both fully implement the DMX512 protocol in hardware and map the DMX channels in the CSR address space.
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The DMX cores are made of a transmitter and receiver cores. Both fully implement the DMX512 protocol in hardware and map the DMX channels in the CSR address space.
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|
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\section{Channel access}
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\section{Channel access}
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Both cores map the 512 DMX channels from addresses 0x000 to 0x7fc. The CSR interface is 32-bit and only the 8 lower bits are significant and represent the DMX channel value; the 24 upper bits are always 0. The first DMX channel is mapped at address 0x000, the second at address 0x004, the third at address 0x008 and so forth.
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Both cores map the 512 DMX channels from addresses 0x000 to 0x7fc. The CSR interface is 32-bit and only the 8 lower bits are significant and represent the DMX channel value; the 24 upper bits are always 0. The first DMX channel is mapped at address 0x000, the second at address 0x004, the third at address 0x008 and so forth.
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|
|
The transmitter core continuously transmits a DMX signal containing the channel data. The channel data can be read and written at any time over the CSR interface without any glitch occuring on the transmitted signal.
|
The transmitter core continuously transmits a DMX signal containing the channel data. The channel data can be read and written at any time over the CSR interface without any glitch occuring on the transmitted signal.
|
|
|
The receiver core continuously tries to receive a DMX signal and updates the channel data. The channel data can be read at any time, and each channel value is updated atomically (i.e. no invalid data is returned if a channel is read over the CSR interface at the same time as it is received).
|
The receiver core continuously tries to receive a DMX signal and updates the channel data. The channel data can be read at any time, and each channel value is updated atomically (i.e. no invalid data is returned if a channel is read over the CSR interface at the same time as it is received).
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|
|
\section{Thru mode}
|
\section{Thru mode}
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To be able to act as a traditional DMX receiving device, the transmitting DMX core can simply forward the incoming DMX signal instead of transmitting the data from the host CPU. This mode is enabled by writing a 1 to the offset 0x800, and disabled (default) by writing 0.
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To be able to act as a traditional DMX receiving device, the transmitting DMX core can simply forward the incoming DMX signal instead of transmitting the data from the host CPU. This mode is enabled by writing a 1 to the offset 0x800, and disabled (default) by writing 0.
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|
|
\section*{Copyright notice}
|
\section*{Copyright notice}
|
Copyright \copyright 2007-2010 S\'ebastien Bourdeauducq. \\
|
Copyright \copyright 2007-2010 S\'ebastien Bourdeauducq. \\
|
Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.3; with no Invariant Sections, no Front-Cover Texts, and no Back-Cover Texts. A copy of the license is included in the LICENSE.FDL file at the root of the Milkymist source distribution.
|
Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.3; with no Invariant Sections, no Front-Cover Texts, and no Back-Cover Texts. A copy of the license is included in the LICENSE.FDL file at the root of the Milkymist source distribution.
|
|
|
\end{document}
|
\end{document}
|
dmx/doc/Makefile 0000644 0001750 0001750 00000000410 11431236177 014237 0 ustar lekernel lekernel TEX=dmx.tex
|
dmx/doc/Makefile 0000644 0001750 0001750 00000000410 11431236177 014237 0 ustar lekernel lekernel TEX=dmx.tex
|
|
|
DVI=$(TEX:.tex=.dvi)
|
DVI=$(TEX:.tex=.dvi)
|
PS=$(TEX:.tex=.ps)
|
PS=$(TEX:.tex=.ps)
|
PDF=$(TEX:.tex=.pdf)
|
PDF=$(TEX:.tex=.pdf)
|
AUX=$(TEX:.tex=.aux)
|
AUX=$(TEX:.tex=.aux)
|
LOG=$(TEX:.tex=.log)
|
LOG=$(TEX:.tex=.log)
|
|
|
all: $(PDF)
|
all: $(PDF)
|
|
|
%.dvi: %.tex
|
%.dvi: %.tex
|
latex $<
|
latex $<
|
|
|
%.ps: %.dvi
|
%.ps: %.dvi
|
dvips $<
|
dvips $<
|
|
|
%.pdf: %.ps
|
%.pdf: %.ps
|
ps2pdf $<
|
ps2pdf $<
|
|
|
clean:
|
clean:
|
rm -f $(DVI) $(PS) $(PDF) $(AUX) $(LOG)
|
rm -f $(DVI) $(PS) $(PDF) $(AUX) $(LOG)
|
|
|
.PHONY: clean
|
.PHONY: clean
|
|
|
