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/////////////////////////////////////////////////////////////////////
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//// ////
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//// FPU ////
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//// Floating Point Unit (Double precision) ////
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//// ////
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//// Author: David Lundgren ////
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//// davidklun@gmail.com ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2009 David Lundgren ////
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//// davidklun@gmail.com ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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`timescale 1ns / 100ps
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module fpu_exceptions( clk, rst, enable, rmode, opa, opb, in_except,
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exponent_in, mantissa_in, fpu_op, out, ex_enable, underflow, overflow,
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inexact, exception, invalid);
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input clk;
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input rst;
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input enable;
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input [1:0] rmode;
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input [63:0] opa;
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input [63:0] opb;
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input [63:0] in_except;
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input [11:0] exponent_in;
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input [1:0] mantissa_in;
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input [2:0] fpu_op;
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output [63:0] out;
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output ex_enable;
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output underflow;
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output overflow;
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output inexact;
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output exception;
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output invalid;
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reg [63:0] out;
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reg ex_enable;
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reg underflow;
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reg overflow;
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reg inexact;
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reg exception;
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reg invalid;
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reg in_et_zero;
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reg opa_et_zero;
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reg opb_et_zero;
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reg input_et_zero;
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reg add;
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reg subtract;
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reg multiply;
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reg divide;
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reg opa_QNaN;
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reg opb_QNaN;
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reg opa_SNaN;
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reg opb_SNaN;
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reg opa_pos_inf;
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reg opb_pos_inf;
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reg opa_neg_inf;
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reg opb_neg_inf;
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reg opa_inf;
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reg opb_inf;
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reg NaN_input;
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reg SNaN_input;
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reg a_NaN;
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reg div_by_0;
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reg div_0_by_0;
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reg div_inf_by_inf;
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reg div_by_inf;
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reg mul_0_by_inf;
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reg mul_inf;
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reg div_inf;
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reg add_inf;
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reg sub_inf;
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reg addsub_inf_invalid;
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reg addsub_inf;
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reg out_inf_trigger;
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reg out_pos_inf;
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reg out_neg_inf;
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reg round_nearest;
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reg round_to_zero;
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reg round_to_pos_inf;
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reg round_to_neg_inf;
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reg inf_round_down_trigger;
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reg mul_uf;
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reg div_uf;
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reg underflow_trigger;
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reg invalid_trigger;
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reg overflow_trigger;
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reg inexact_trigger;
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reg except_trigger;
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reg enable_trigger;
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reg NaN_out_trigger;
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reg SNaN_trigger;
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wire [10:0] exp_2047 = 11'b11111111111;
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wire [10:0] exp_2046 = 11'b11111111110;
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reg [62:0] NaN_output_0;
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reg [62:0] NaN_output;
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wire [51:0] mantissa_max = 52'b1111111111111111111111111111111111111111111111111111;
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reg [62:0] inf_round_down;
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reg [62:0] out_inf;
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reg [63:0] out_0;
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reg [63:0] out_1;
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reg [63:0] out_2;
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always @(posedge clk)
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begin
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if (rst) begin
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in_et_zero <= 0;
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opa_et_zero <= 0;
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opb_et_zero <= 0;
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input_et_zero <= 0;
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add <= 0;
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subtract <= 0;
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multiply <= 0;
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divide <= 0;
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opa_QNaN <= 0;
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opb_QNaN <= 0;
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opa_SNaN <= 0;
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opb_SNaN <= 0;
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opa_pos_inf <= 0;
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opb_pos_inf <= 0;
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opa_neg_inf <= 0;
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opb_neg_inf <= 0;
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opa_inf <= 0;
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opb_inf <= 0;
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NaN_input <= 0;
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SNaN_input <= 0;
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a_NaN <= 0;
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div_by_0 <= 0;
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div_0_by_0 <= 0;
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div_inf_by_inf <= 0;
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div_by_inf <= 0;
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mul_0_by_inf <= 0;
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mul_inf <= 0;
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div_inf <= 0;
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add_inf <= 0;
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sub_inf <= 0;
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addsub_inf_invalid <= 0;
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addsub_inf <= 0;
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out_inf_trigger <= 0;
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out_pos_inf <= 0;
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out_neg_inf <= 0;
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round_nearest <= 0;
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round_to_zero <= 0;
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round_to_pos_inf <= 0;
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round_to_neg_inf <= 0;
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inf_round_down_trigger <= 0;
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mul_uf <= 0;
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div_uf <= 0;
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underflow_trigger <= 0;
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invalid_trigger <= 0;
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overflow_trigger <= 0;
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inexact_trigger <= 0;
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except_trigger <= 0;
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enable_trigger <= 0;
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NaN_out_trigger <= 0;
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SNaN_trigger <= 0;
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NaN_output_0 <= 0;
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NaN_output <= 0;
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inf_round_down <= 0;
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out_inf <= 0;
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out_0 <= 0;
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out_1 <= 0;
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out_2 <= 0;
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end
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else if (enable) begin
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in_et_zero <= !(|in_except[62:0]);
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opa_et_zero <= !(|opa[62:0]);
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opb_et_zero <= !(|opb[62:0]);
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input_et_zero <= !(|in_except[62:0]);
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add <= fpu_op == 3'b000;
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subtract <= fpu_op == 3'b001;
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multiply <= fpu_op == 3'b010;
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divide <= fpu_op == 3'b011;
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opa_QNaN <= (opa[62:52] == 2047) & |opa[51:0] & opa[51];
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opb_QNaN <= (opb[62:52] == 2047) & |opb[51:0] & opb[51];
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opa_SNaN <= (opa[62:52] == 2047) & |opa[51:0] & !opa[51];
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opb_SNaN <= (opb[62:52] == 2047) & |opb[51:0] & !opb[51];
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opa_pos_inf <= !opa[63] & (opa[62:52] == 2047) & !(|opa[51:0]);
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opb_pos_inf <= !opb[63] & (opb[62:52] == 2047) & !(|opb[51:0]);
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opa_neg_inf <= opa[63] & (opa[62:52] == 2047) & !(|opa[51:0]);
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opb_neg_inf <= opb[63] & (opb[62:52] == 2047) & !(|opb[51:0]);
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opa_inf <= (opa[62:52] == 2047) & !(|opa[51:0]);
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opb_inf <= (opb[62:52] == 2047) & !(|opb[51:0]);
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NaN_input <= opa_QNaN | opb_QNaN | opa_SNaN | opb_SNaN;
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SNaN_input <= opa_SNaN | opb_SNaN;
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a_NaN <= opa_QNaN | opa_SNaN;
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div_by_0 <= divide & opb_et_zero & !opa_et_zero;
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div_0_by_0 <= divide & opb_et_zero & opa_et_zero;
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div_inf_by_inf <= divide & opa_inf & opb_inf;
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div_by_inf <= divide & !opa_inf & opb_inf;
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mul_0_by_inf <= multiply & ((opa_inf & opb_et_zero) | (opa_et_zero & opb_inf));
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mul_inf <= multiply & (opa_inf | opb_inf) & !mul_0_by_inf;
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div_inf <= divide & opa_inf & !opb_inf;
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add_inf <= (add & (opa_inf | opb_inf));
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sub_inf <= (subtract & (opa_inf | opb_inf));
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addsub_inf_invalid <= (add & opa_pos_inf & opb_neg_inf) | (add & opa_neg_inf & opb_pos_inf) |
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(subtract & opa_pos_inf & opb_pos_inf) | (subtract & opa_neg_inf & opb_neg_inf);
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addsub_inf <= (add_inf | sub_inf) & !addsub_inf_invalid;
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out_inf_trigger <= addsub_inf | mul_inf | div_inf | div_by_0 | (exponent_in > 2046);
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out_pos_inf <= out_inf_trigger & !in_except[63];
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out_neg_inf <= out_inf_trigger & in_except[63];
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round_nearest <= (rmode == 2'b00);
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round_to_zero <= (rmode == 2'b01);
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round_to_pos_inf <= (rmode == 2'b10);
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round_to_neg_inf <= (rmode == 2'b11);
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inf_round_down_trigger <= (out_pos_inf & round_to_neg_inf) |
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(out_neg_inf & round_to_pos_inf) |
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(out_inf_trigger & round_to_zero);
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mul_uf <= multiply & !opa_et_zero & !opb_et_zero & in_et_zero;
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div_uf <= divide & !opa_et_zero & in_et_zero;
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underflow_trigger <= div_by_inf | mul_uf | div_uf;
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invalid_trigger <= SNaN_input | addsub_inf_invalid | mul_0_by_inf |
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div_0_by_0 | div_inf_by_inf;
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overflow_trigger <= out_inf_trigger & !NaN_input;
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inexact_trigger <= (|mantissa_in[1:0] | out_inf_trigger | underflow_trigger) &
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!NaN_input;
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except_trigger <= invalid_trigger | overflow_trigger | underflow_trigger |
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inexact_trigger;
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enable_trigger <= except_trigger | out_inf_trigger | NaN_input;
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NaN_out_trigger <= NaN_input | invalid_trigger;
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SNaN_trigger <= invalid_trigger & !SNaN_input;
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NaN_output_0 <= a_NaN ? { exp_2047, 1'b1, opa[50:0]} : { exp_2047, 1'b1, opb[50:0]};
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NaN_output <= SNaN_trigger ? { exp_2047, 2'b01, opa[49:0]} : NaN_output_0;
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inf_round_down <= { exp_2046, mantissa_max };
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out_inf <= inf_round_down_trigger ? inf_round_down : { exp_2047, 52'b0 };
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out_0 <= underflow_trigger ? { in_except[63], 63'b0 } : in_except;
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out_1 <= out_inf_trigger ? { in_except[63], out_inf } : out_0;
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out_2 <= NaN_out_trigger ? { in_except[63], NaN_output} : out_1;
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end
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end
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always @(posedge clk)
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begin
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if (rst) begin
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ex_enable <= 0;
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underflow <= 0;
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overflow <= 0;
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inexact <= 0;
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exception <= 0;
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invalid <= 0;
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out <= 0;
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end
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else if (enable) begin
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ex_enable <= enable_trigger;
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underflow <= underflow_trigger;
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overflow <= overflow_trigger;
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inexact <= inexact_trigger;
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exception <= except_trigger;
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invalid <= invalid_trigger;
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out <= out_2;
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end
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end
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endmodule
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