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[/] [eco32/] [trunk/] [fpga/] [experiments/] [memctrl/] [sim/] [memctrl-0/] [ramctrl/] [ram.v] - Diff between revs 312 and 326

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Rev 312 Rev 326
Line 9... Line 9...
 
 
 
 
//
//
// use this set of parameters for minimal access times
// use this set of parameters for minimal access times
//
//
`define RD_CYCLES       4'd2    // # cycles for read, min = 2
//`define RD_CYCLES     4'd2    // # cycles for read, min = 2
`define WR_CYCLES       4'd2    // # cycles for write, min = 2
//`define WR_CYCLES     4'd2    // # cycles for write, min = 2
 
 
//
//
// use this set of parameters for realistic access times
// use this set of parameters for realistic access times
//
//
//`define RD_CYCLES     4'd14   // # cycles for read, min = 2
`define RD_CYCLES       4'd6    // # cycles for read, min = 2
//`define WR_CYCLES     4'd6    // # cycles for write, min = 2
`define WR_CYCLES       4'd4    // # cycles for write, min = 2
 
 
 
 
module ram(clk, rst,
module ram(clk, rst,
           stb, we, addr,
           stb, we, addr,
           data_in, data_out, ack);
           data_in, data_out, ack);

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