//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// User_input_sim.v ////
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//// User_input_sim.v ////
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//// ////
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//// ////
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//// This file is part of the Ethernet IP core project ////
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//// This file is part of the Ethernet IP core project ////
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//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
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//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Jon Gao (gaojon@yahoo.com) ////
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//// - Jon Gao (gaojon@yahoo.com) ////
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//// ////
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//// ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2001 Authors ////
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//// Copyright (C) 2001 Authors ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.3 2006/11/17 17:53:07 maverickist
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// Revision 1.3 2006/11/17 17:53:07 maverickist
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// no message
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// no message
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//
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//
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// Revision 1.2 2006/01/19 14:07:50 maverickist
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// Revision 1.2 2006/01/19 14:07:50 maverickist
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// verification is complete.
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// verification is complete.
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//
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//
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// Revision 1.2 2005/12/13 12:15:35 Administrator
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// Revision 1.2 2005/12/13 12:15:35 Administrator
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// no message
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// no message
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//
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//
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// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator
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// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator
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// no message
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// no message
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//
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//
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module User_int_sim (
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module User_int_sim (
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Reset ,
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Reset ,
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Clk_user ,
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Clk_user ,
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CPU_init_end ,
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CPU_init_end ,
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//user inputerface ,
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//user inputerface ,
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Rx_mac_ra ,
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Rx_mac_ra ,
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Rx_mac_rd ,
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Rx_mac_rd ,
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Rx_mac_data ,
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Rx_mac_data ,
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Rx_mac_BE ,
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Rx_mac_BE ,
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Rx_mac_pa ,
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Rx_mac_pa ,
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Rx_mac_sop ,
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Rx_mac_sop ,
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Rx_mac_eop ,
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Rx_mac_eop ,
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//user inputerface ,
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//user inputerface ,
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Tx_mac_wa ,
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Tx_mac_wa ,
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Tx_mac_wr ,
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Tx_mac_wr ,
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Tx_mac_data ,
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Tx_mac_data ,
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Tx_mac_BE ,
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Tx_mac_BE ,
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Tx_mac_sop ,
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Tx_mac_sop ,
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Tx_mac_eop
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Tx_mac_eop
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);
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);
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input Reset ;
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input Reset ;
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input Clk_user ;
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input Clk_user ;
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input CPU_init_end ;
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input CPU_init_end ;
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//user inputerface
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//user inputerface
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input Rx_mac_ra ;
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input Rx_mac_ra ;
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output Rx_mac_rd ;
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output Rx_mac_rd ;
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input [31:0] Rx_mac_data ;
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input [31:0] Rx_mac_data ;
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input [1:0] Rx_mac_BE ;
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input [1:0] Rx_mac_BE ;
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input Rx_mac_pa ;
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input Rx_mac_pa ;
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input Rx_mac_sop ;
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input Rx_mac_sop ;
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input Rx_mac_eop ;
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input Rx_mac_eop ;
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//user inputerface
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//user inputerface
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input Tx_mac_wa ;
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input Tx_mac_wa ;
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output Tx_mac_wr ;
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output Tx_mac_wr ;
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output [31:0] Tx_mac_data ;
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output [31:0] Tx_mac_data ;
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output [1:0] Tx_mac_BE ;//big endian
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output [1:0] Tx_mac_BE ;//big endian
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output Tx_mac_sop ;
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output Tx_mac_sop ;
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output Tx_mac_eop ;
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output Tx_mac_eop ;
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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// inputernal signals
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// inputernal signals
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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reg[4:0] operation;
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reg[4:0] operation;
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reg[31:0] data;
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reg[31:0] data;
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reg Rx_mac_rd;
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reg Rx_mac_rd;
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reg Start_tran;
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reg Start_tran;
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//generate Tx user data
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//generate Tx user data
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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initial
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initial
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begin
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begin
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operation =0;
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operation =0;
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data =0;
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data =0;
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end
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end
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always @ (posedge Clk_user or posedge Reset)
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always @ (posedge Clk_user or posedge Reset)
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if (Reset)
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if (Reset)
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Start_tran <=0;
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Start_tran <=0;
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else if (Tx_mac_eop&&!Tx_mac_wa)
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else if (Tx_mac_eop&&!Tx_mac_wa)
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Start_tran <=0;
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Start_tran <=0;
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else if (Tx_mac_wa)
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else if (Tx_mac_wa)
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Start_tran <=1;
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Start_tran <=1;
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always @ (posedge Clk_user)
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always @ (posedge Clk_user)
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if (Tx_mac_wa&&CPU_init_end)
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if (Tx_mac_wa&&CPU_init_end)
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$ip_32W_gen("../data/config.ini",operation,data);
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$ip_32W_gen("../data/config.ini",operation,data);
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else
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else
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begin
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begin
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operation <=0;
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operation <=0;
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data <=0;
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data <=0;
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end
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end
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assign Tx_mac_data =data;
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assign Tx_mac_data =data;
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assign Tx_mac_wr =operation[4];
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assign Tx_mac_wr =operation[4];
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assign Tx_mac_sop =operation[3];
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assign Tx_mac_sop =operation[3];
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assign Tx_mac_eop =operation[2];
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assign Tx_mac_eop =operation[2];
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assign Tx_mac_BE =operation[1:0];
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assign Tx_mac_BE =operation[1:0];
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//verify Rx user data
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//verify Rx user data
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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always @ (posedge Clk_user or posedge Reset)
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always @ (posedge Clk_user or posedge Reset)
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if (Reset)
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if (Reset)
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Rx_mac_rd <=0;
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Rx_mac_rd <=0;
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else if(Rx_mac_ra&Rx_mac_rd==0)
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else if(Rx_mac_ra&Rx_mac_rd==0)
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//else if(Rx_mac_ra)
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//else if(Rx_mac_ra)
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Rx_mac_rd <=1;
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Rx_mac_rd <=1;
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else
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else
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Rx_mac_rd <=0;
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Rx_mac_rd <=0;
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always @ (posedge Clk_user )
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always @ (posedge Clk_user )
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if (Rx_mac_pa)
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if (Rx_mac_pa)
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$ip_32W_check( Rx_mac_data,
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$ip_32W_check( Rx_mac_data,
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{Rx_mac_sop,Rx_mac_eop,Rx_mac_eop?Rx_mac_BE:2'b0});
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{Rx_mac_sop,Rx_mac_eop,Rx_mac_eop?Rx_mac_BE:2'b0});
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endmodule
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endmodule
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