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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.29 2002/11/19 18:13:49 mohor
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// r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead.
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//
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// Revision 1.28 2002/11/15 14:27:15 mohor
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// Revision 1.28 2002/11/15 14:27:15 mohor
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// Since r_Rst bit is not used any more, default value is changed to 0xa000.
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// Since r_Rst bit is not used any more, default value is changed to 0xa000.
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//
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//
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// Revision 1.27 2002/11/01 18:19:34 mohor
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// Revision 1.27 2002/11/01 18:19:34 mohor
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// Defines fixed to use generic RAM by default.
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// Defines fixed to use generic RAM by default.
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Line 261... |
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// WISHBONE interface is Revision B3 compliant (uncomment when needed)
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// WISHBONE interface is Revision B3 compliant (uncomment when needed)
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//`define ETH_WISHBONE_B3
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//`define ETH_WISHBONE_B3
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// Following defines are needed when eth_cop.v is used. Otherwise they may be deleted.
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`define ETH_BASE 32'hd0000000
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`define ETH_WIDTH 32'h800
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`define MEMORY_BASE 32'h2000
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`define MEMORY_WIDTH 32'h10000
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`define M1_ADDRESSED_S1 ( (m1_wb_adr_i >= `ETH_BASE) & (m1_wb_adr_i < (`ETH_BASE + `ETH_WIDTH )) )
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`define M1_ADDRESSED_S2 ( (m1_wb_adr_i >= `MEMORY_BASE) & (m1_wb_adr_i < (`MEMORY_BASE + `MEMORY_WIDTH)) )
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`define M2_ADDRESSED_S1 ( (m2_wb_adr_i >= `ETH_BASE) & (m2_wb_adr_i < (`ETH_BASE + `ETH_WIDTH )) )
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`define M2_ADDRESSED_S2 ( (m2_wb_adr_i >= `MEMORY_BASE) & (m2_wb_adr_i < (`MEMORY_BASE + `MEMORY_WIDTH)) )
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// Previous defines are only needed for eth_cop.v
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No newline at end of file
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