| Line 39... |
Line 39... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.30 2003/06/13 11:55:37 mohor
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// Define file in eth_cop.v is changed to eth_defines.v. Some defines were
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// moved from tb_eth_defines.v to eth_defines.v.
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//
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// Revision 1.29 2002/11/19 18:13:49 mohor
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// Revision 1.29 2002/11/19 18:13:49 mohor
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// r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead.
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// r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead.
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//
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//
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// Revision 1.28 2002/11/15 14:27:15 mohor
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// Revision 1.28 2002/11/15 14:27:15 mohor
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// Since r_Rst bit is not used any more, default value is changed to 0xa000.
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// Since r_Rst bit is not used any more, default value is changed to 0xa000.
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| Line 171... |
Line 175... |
// Core is going to be implemented in Virtex FPGA and contains Virtex
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// Core is going to be implemented in Virtex FPGA and contains Virtex
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// specific elements.
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// specific elements.
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// Ethernet implemented in ASIC with Virtual Silicon RAMs
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// Ethernet implemented in ASIC with Virtual Silicon RAMs
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// `define ETH_VIRTUAL_SILICON_RAM // Virtual Silicon RAMS used storing buffer decriptors (ASIC implementation)
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// `define ETH_VIRTUAL_SILICON_RAM // Virtual Silicon RAMS used storing buffer decriptors (ASIC implementation)
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// `define ETH_ARTISAN_RAM // Artisan RAMS used storing buffer decriptors (ASIC implementation)
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`define ETH_MODER_ADR 8'h0 // 0x0
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`define ETH_MODER_ADR 8'h0 // 0x0
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`define ETH_INT_SOURCE_ADR 8'h1 // 0x4
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`define ETH_INT_SOURCE_ADR 8'h1 // 0x4
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`define ETH_INT_MASK_ADR 8'h2 // 0x8
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`define ETH_INT_MASK_ADR 8'h2 // 0x8
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`define ETH_IPGT_ADR 8'h3 // 0xC
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`define ETH_IPGT_ADR 8'h3 // 0xC
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