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Line 39... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.33 2003/11/12 18:24:58 tadejm
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// WISHBONE slave changed and tested from only 32-bit accesss to byte access.
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//
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// Revision 1.32 2003/10/17 07:46:13 markom
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// Revision 1.32 2003/10/17 07:46:13 markom
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// mbist signals updated according to newest convention
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// mbist signals updated according to newest convention
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//
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//
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// Revision 1.31 2003/08/14 16:42:58 simons
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// Revision 1.31 2003/08/14 16:42:58 simons
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// Artisan ram instance added.
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// Artisan ram instance added.
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Line 177... |
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//`define ETH_BIST // Bist for usage with Virtual Silicon RAMS
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//`define ETH_BIST // Bist for usage with Virtual Silicon RAMS
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`define ETH_MBIST_CTRL_WIDTH 3 // width of MBIST control bus
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`define ETH_MBIST_CTRL_WIDTH 3 // width of MBIST control bus
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// Ethernet implemented in Xilinx Chips
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// Ethernet implemented in Xilinx Chips (uncomment following lines)
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// `define ETH_FIFO_XILINX // Use Xilinx distributed ram for tx and rx fifo
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// `define ETH_FIFO_XILINX // Use Xilinx distributed ram for tx and rx fifo
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// `define ETH_XILINX_RAMB4 // Selection of the used memory for Buffer descriptors
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// `define ETH_XILINX_RAMB4 // Selection of the used memory for Buffer descriptors
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// Core is going to be implemented in Virtex FPGA and contains Virtex
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// Core is going to be implemented in Virtex FPGA and contains Virtex
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// specific elements.
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// specific elements.
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// Ethernet implemented in Altera Chips (uncomment following lines)
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//`define ETH_ALTERA_ALTSYNCRAM
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// Ethernet implemented in ASIC with Virtual Silicon RAMs
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// Ethernet implemented in ASIC with Virtual Silicon RAMs
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// `define ETH_VIRTUAL_SILICON_RAM // Virtual Silicon RAMS used storing buffer decriptors (ASIC implementation)
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// `define ETH_VIRTUAL_SILICON_RAM // Virtual Silicon RAMS used storing buffer decriptors (ASIC implementation)
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// Ethernet implemented in ASIC with Artisan RAMs
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// `define ETH_ARTISAN_RAM // Artisan RAMS used storing buffer decriptors (ASIC implementation)
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// `define ETH_ARTISAN_RAM // Artisan RAMS used storing buffer decriptors (ASIC implementation)
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// Uncomment when Avalon bus is used
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//`define ETH_AVALON_BUS
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`define ETH_MODER_ADR 8'h0 // 0x0
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`define ETH_MODER_ADR 8'h0 // 0x0
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`define ETH_INT_SOURCE_ADR 8'h1 // 0x4
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`define ETH_INT_SOURCE_ADR 8'h1 // 0x4
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`define ETH_INT_MASK_ADR 8'h2 // 0x8
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`define ETH_INT_MASK_ADR 8'h2 // 0x8
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`define ETH_IPGT_ADR 8'h3 // 0xC
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`define ETH_IPGT_ADR 8'h3 // 0xC
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`define ETH_IPGR1_ADR 8'h4 // 0x10
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`define ETH_IPGR1_ADR 8'h4 // 0x10
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