| Line 39... |
Line 39... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.21 2002/09/10 10:35:23 mohor
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// Ethernet debug registers removed.
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//
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// Revision 1.20 2002/09/04 18:40:25 mohor
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// Revision 1.20 2002/09/04 18:40:25 mohor
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// ETH_TXCTRL and ETH_RXCTRL registers added. Interrupts related to
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// ETH_TXCTRL and ETH_RXCTRL registers added. Interrupts related to
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// the control frames connected.
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// the control frames connected.
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//
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//
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// Revision 1.19 2002/08/19 16:01:40 mohor
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// Revision 1.19 2002/08/19 16:01:40 mohor
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| Line 135... |
Line 138... |
`include "timescale.v"
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`include "timescale.v"
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module eth_registers( DataIn, Address, Rw, Cs, Clk, Reset, DataOut,
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module eth_registers( DataIn, Address, Rw, Cs, Clk, Reset, DataOut,
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r_RecSmall, r_Pad, r_HugEn, r_CrcEn, r_DlyCrcEn,
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r_RecSmall, r_Pad, r_HugEn, r_CrcEn, r_DlyCrcEn,
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r_Rst, r_FullD, r_ExDfrEn, r_NoBckof, r_LoopBck, r_IFG,
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r_FullD, r_ExDfrEn, r_NoBckof, r_LoopBck, r_IFG,
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r_Pro, r_Iam, r_Bro, r_NoPre, r_TxEn, r_RxEn,
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r_Pro, r_Iam, r_Bro, r_NoPre, r_TxEn, r_RxEn,
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TxB_IRQ, TxE_IRQ, RxB_IRQ, RxE_IRQ, Busy_IRQ,
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TxB_IRQ, TxE_IRQ, RxB_IRQ, RxE_IRQ, Busy_IRQ,
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r_IPGT, r_IPGR1, r_IPGR2, r_MinFL, r_MaxFL, r_MaxRet,
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r_IPGT, r_IPGR1, r_IPGR2, r_MinFL, r_MaxFL, r_MaxRet,
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r_CollValid, r_TxFlow, r_RxFlow, r_PassAll,
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r_CollValid, r_TxFlow, r_RxFlow, r_PassAll,
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r_MiiMRst, r_MiiNoPre, r_ClkDiv, r_WCtrlData, r_RStat, r_ScanStat,
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r_MiiMRst, r_MiiNoPre, r_ClkDiv, r_WCtrlData, r_RStat, r_ScanStat,
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Line 175... |
output r_RecSmall;
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output r_RecSmall;
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output r_Pad;
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output r_Pad;
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output r_HugEn;
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output r_HugEn;
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output r_CrcEn;
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output r_CrcEn;
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output r_DlyCrcEn;
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output r_DlyCrcEn;
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output r_Rst;
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output r_FullD;
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output r_FullD;
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output r_ExDfrEn;
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output r_ExDfrEn;
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output r_NoBckof;
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output r_NoBckof;
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output r_LoopBck;
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output r_LoopBck;
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output r_IFG;
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output r_IFG;
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| Line 649... |
Line 651... |
assign r_RecSmall = MODEROut[16];
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assign r_RecSmall = MODEROut[16];
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assign r_Pad = MODEROut[15];
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assign r_Pad = MODEROut[15];
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assign r_HugEn = MODEROut[14];
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assign r_HugEn = MODEROut[14];
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assign r_CrcEn = MODEROut[13];
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assign r_CrcEn = MODEROut[13];
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assign r_DlyCrcEn = MODEROut[12];
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assign r_DlyCrcEn = MODEROut[12];
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assign r_Rst = MODEROut[11];
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// assign r_Rst = MODEROut[11]; This signal is not used any more
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assign r_FullD = MODEROut[10];
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assign r_FullD = MODEROut[10];
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assign r_ExDfrEn = MODEROut[9];
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assign r_ExDfrEn = MODEROut[9];
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assign r_NoBckof = MODEROut[8];
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assign r_NoBckof = MODEROut[8];
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assign r_LoopBck = MODEROut[7];
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assign r_LoopBck = MODEROut[7];
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assign r_IFG = MODEROut[6];
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assign r_IFG = MODEROut[6];
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