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Line 39... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.28 2004/04/26 15:26:23 igorm
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// - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the
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// previous update of the core.
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// - TxBDAddress is set to 0 after the TX is enabled in the MODER register.
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// - RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER
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// register. (thanks to Mathias and Torbjorn)
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// - Multicast reception was fixed. Thanks to Ulrich Gries
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//
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// Revision 1.27 2004/04/26 11:42:17 igorm
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// Revision 1.27 2004/04/26 11:42:17 igorm
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// TX_BD_NUM_Wr error fixed. Error was entered with the last check-in.
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// TX_BD_NUM_Wr error fixed. Error was entered with the last check-in.
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//
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//
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// Revision 1.26 2003/11/12 18:24:59 tadejm
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// Revision 1.26 2003/11/12 18:24:59 tadejm
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// WISHBONE slave changed and tested from only 32-bit accesss to byte access.
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// WISHBONE slave changed and tested from only 32-bit accesss to byte access.
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Line 325... |
Line 333... |
wire [3:0] MAC_ADDR0_Wr;
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wire [3:0] MAC_ADDR0_Wr;
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wire [1:0] MAC_ADDR1_Wr;
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wire [1:0] MAC_ADDR1_Wr;
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wire [3:0] HASH0_Wr;
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wire [3:0] HASH0_Wr;
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wire [3:0] HASH1_Wr;
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wire [3:0] HASH1_Wr;
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wire [2:0] TXCTRL_Wr;
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wire [2:0] TXCTRL_Wr;
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wire [1:0] RXCTRL_Wr;
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wire [0:0] TX_BD_NUM_Wr;
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wire [0:0] TX_BD_NUM_Wr;
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assign MODER_Wr[0] = Write[0] & MODER_Sel;
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assign MODER_Wr[0] = Write[0] & MODER_Sel;
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assign MODER_Wr[1] = Write[1] & MODER_Sel;
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assign MODER_Wr[1] = Write[1] & MODER_Sel;
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assign MODER_Wr[2] = Write[2] & MODER_Sel;
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assign MODER_Wr[2] = Write[2] & MODER_Sel;
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Line 370... |
Line 377... |
assign HASH1_Wr[2] = Write[2] & HASH1_Sel;
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assign HASH1_Wr[2] = Write[2] & HASH1_Sel;
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assign HASH1_Wr[3] = Write[3] & HASH1_Sel;
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assign HASH1_Wr[3] = Write[3] & HASH1_Sel;
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assign TXCTRL_Wr[0] = Write[0] & TXCTRL_Sel;
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assign TXCTRL_Wr[0] = Write[0] & TXCTRL_Sel;
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assign TXCTRL_Wr[1] = Write[1] & TXCTRL_Sel;
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assign TXCTRL_Wr[1] = Write[1] & TXCTRL_Sel;
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assign TXCTRL_Wr[2] = Write[2] & TXCTRL_Sel;
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assign TXCTRL_Wr[2] = Write[2] & TXCTRL_Sel;
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assign RXCTRL_Wr[0] = Write[0] & RXCTRL_Sel;
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assign RXCTRL_Wr[1] = Write[1] & RXCTRL_Sel;
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assign TX_BD_NUM_Wr[0] = Write[0] & TX_BD_NUM_Sel & (DataIn<='h80);
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assign TX_BD_NUM_Wr[0] = Write[0] & TX_BD_NUM_Sel & (DataIn<='h80);
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wire [31:0] MODEROut;
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wire [31:0] MODEROut;
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Line 397... |
Line 402... |
wire [31:0] MAC_ADDR1Out;
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wire [31:0] MAC_ADDR1Out;
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wire [31:0] TX_BD_NUMOut;
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wire [31:0] TX_BD_NUMOut;
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wire [31:0] HASH0Out;
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wire [31:0] HASH0Out;
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wire [31:0] HASH1Out;
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wire [31:0] HASH1Out;
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wire [31:0] TXCTRLOut;
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wire [31:0] TXCTRLOut;
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wire [31:0] RXCTRLOut;
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// MODER Register
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// MODER Register
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eth_register #(`ETH_MODER_WIDTH_0, `ETH_MODER_DEF_0) MODER_0
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eth_register #(`ETH_MODER_WIDTH_0, `ETH_MODER_DEF_0) MODER_0
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(
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(
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.DataIn (DataIn[`ETH_MODER_WIDTH_0 - 1:0]),
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.DataIn (DataIn[`ETH_MODER_WIDTH_0 - 1:0]),
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Line 832... |
Line 836... |
.Reset (Reset),
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.Reset (Reset),
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.SyncReset (RstTxPauseRq)
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.SyncReset (RstTxPauseRq)
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);
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);
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assign TXCTRLOut[31:`ETH_TX_CTRL_WIDTH_2 + 16] = 0;
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assign TXCTRLOut[31:`ETH_TX_CTRL_WIDTH_2 + 16] = 0;
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// RXCTRL Register
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eth_register #(`ETH_RX_CTRL_WIDTH_0, `ETH_RX_CTRL_DEF_0) RXCTRL_0
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(
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.DataIn (DataIn[`ETH_RX_CTRL_WIDTH_0 - 1:0]),
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.DataOut (RXCTRLOut[`ETH_RX_CTRL_WIDTH_0 - 1:0]),
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.Write (RXCTRL_Wr[0]),
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.Clk (Clk),
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.Reset (Reset),
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.SyncReset (1'b0)
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);
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eth_register #(`ETH_RX_CTRL_WIDTH_1, `ETH_RX_CTRL_DEF_1) RXCTRL_1
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(
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.DataIn (DataIn[`ETH_RX_CTRL_WIDTH_1 + 7:8]),
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.DataOut (RXCTRLOut[`ETH_RX_CTRL_WIDTH_1 + 7:8]),
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.Write (RXCTRL_Wr[1]),
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.Clk (Clk),
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.Reset (Reset),
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.SyncReset (1'b0)
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);
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assign RXCTRLOut[31:`ETH_RX_CTRL_WIDTH_1 + 8] = 0;
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// Reading data from registers
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// Reading data from registers
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always @ (Address or Read or MODEROut or INT_SOURCEOut or
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always @ (Address or Read or MODEROut or INT_SOURCEOut or
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INT_MASKOut or IPGTOut or IPGR1Out or IPGR2Out or
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INT_MASKOut or IPGTOut or IPGR1Out or IPGR2Out or
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PACKETLENOut or COLLCONFOut or CTRLMODEROut or MIIMODEROut or
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PACKETLENOut or COLLCONFOut or CTRLMODEROut or MIIMODEROut or
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MIICOMMANDOut or MIIADDRESSOut or MIITX_DATAOut or MIIRX_DATAOut or
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MIICOMMANDOut or MIIADDRESSOut or MIITX_DATAOut or MIIRX_DATAOut or
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MIISTATUSOut or MAC_ADDR0Out or MAC_ADDR1Out or TX_BD_NUMOut or
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MIISTATUSOut or MAC_ADDR0Out or MAC_ADDR1Out or TX_BD_NUMOut or
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HASH0Out or HASH1Out or TXCTRLOut or RXCTRLOut
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HASH0Out or HASH1Out or TXCTRLOut
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)
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)
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begin
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begin
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if(Read) // read
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if(Read) // read
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begin
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begin
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case(Address)
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case(Address)
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Line 887... |
Line 871... |
`ETH_MAC_ADDR1_ADR : DataOut<=MAC_ADDR1Out;
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`ETH_MAC_ADDR1_ADR : DataOut<=MAC_ADDR1Out;
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`ETH_TX_BD_NUM_ADR : DataOut<=TX_BD_NUMOut;
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`ETH_TX_BD_NUM_ADR : DataOut<=TX_BD_NUMOut;
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`ETH_HASH0_ADR : DataOut<=HASH0Out;
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`ETH_HASH0_ADR : DataOut<=HASH0Out;
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`ETH_HASH1_ADR : DataOut<=HASH1Out;
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`ETH_HASH1_ADR : DataOut<=HASH1Out;
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`ETH_TX_CTRL_ADR : DataOut<=TXCTRLOut;
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`ETH_TX_CTRL_ADR : DataOut<=TXCTRLOut;
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`ETH_RX_CTRL_ADR : DataOut<=RXCTRLOut;
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default: DataOut<=32'h0;
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default: DataOut<=32'h0;
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endcase
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endcase
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end
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end
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else
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else
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