| Line 39... |
Line 39... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.6 2003/10/17 07:46:15 markom
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// mbist signals updated according to newest convention
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//
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// Revision 1.5 2003/08/14 16:42:58 simons
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// Revision 1.5 2003/08/14 16:42:58 simons
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// Artisan ram instance added.
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// Artisan ram instance added.
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//
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//
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// Revision 1.4 2002/10/18 17:04:20 tadejm
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// Revision 1.4 2002/10/18 17:04:20 tadejm
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// Changed BIST scan signals.
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// Changed BIST scan signals.
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| Line 82... |
Line 85... |
// Generic synchronous single-port RAM interface
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// Generic synchronous single-port RAM interface
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//
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//
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input clk; // Clock, rising edge
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input clk; // Clock, rising edge
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input rst; // Reset, active high
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input rst; // Reset, active high
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input ce; // Chip enable input, active high
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input ce; // Chip enable input, active high
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input we; // Write enable input, active high
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input [3:0] we; // Write enable input, active high
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input oe; // Output enable input, active high
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input oe; // Output enable input, active high
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input [7:0] addr; // address bus inputs
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input [7:0] addr; // address bus inputs
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input [31:0] di; // input data bus
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input [31:0] di; // input data bus
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output [31:0] do; // output data bus
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output [31:0] do; // output data bus
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| Line 97... |
Line 100... |
input [`ETH_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
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input [`ETH_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
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`endif
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`endif
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`ifdef ETH_XILINX_RAMB4
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`ifdef ETH_XILINX_RAMB4
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RAMB4_S16 ram0
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/*RAMB4_S16 ram0
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(
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.DO (do[15:0]),
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.ADDR (addr),
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.DI (di[15:0]),
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.EN (ce),
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.CLK (clk),
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.WE (we),
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.RST (rst)
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);
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RAMB4_S16 ram1
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(
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.DO (do[31:16]),
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.ADDR (addr),
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.DI (di[31:16]),
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.EN (ce),
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.CLK (clk),
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.WE (we),
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.RST (rst)
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);*/
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RAMB4_S8 ram0
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(
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(
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.DO (do[15:0]),
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.DO (do[7:0]),
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.ADDR (addr),
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.ADDR (addr),
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.DI (di[15:0]),
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.DI (di[7:0]),
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.EN (ce),
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.EN (ce),
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.CLK (clk),
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.CLK (clk),
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.WE (we),
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.WE (we[0]),
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.RST (rst)
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.RST (rst)
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);
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);
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RAMB4_S16 ram1
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RAMB4_S8 ram1
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(
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(
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.DO (do[31:16]),
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.DO (do[15:8]),
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.ADDR (addr),
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.ADDR (addr),
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.DI (di[31:16]),
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.DI (di[15:8]),
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.EN (ce),
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.EN (ce),
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.CLK (clk),
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.CLK (clk),
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.WE (we),
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.WE (we[1]),
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.RST (rst)
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);
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RAMB4_S8 ram2
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(
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.DO (do[23:16]),
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.ADDR (addr),
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.DI (di[23:16]),
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.EN (ce),
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.CLK (clk),
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.WE (we[2]),
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.RST (rst)
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);
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RAMB4_S8 ram3
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(
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.DO (do[31:24]),
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.ADDR (addr),
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.DI (di[31:24]),
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.EN (ce),
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.CLK (clk),
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.WE (we[3]),
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.RST (rst)
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.RST (rst)
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);
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);
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`else // !ETH_XILINX_RAMB4
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`else // !ETH_XILINX_RAMB4
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`ifdef ETH_VIRTUAL_SILICON_RAM
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`ifdef ETH_VIRTUAL_SILICON_RAM
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`ifdef ETH_BIST
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`ifdef ETH_BIST
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vs_hdsp_256x32_bist ram0_bist
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//vs_hdsp_256x32_bist ram0_bist
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vs_hdsp_256x32_bw_bist ram0_bist
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`else
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`else
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vs_hdsp_256x32 ram0
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//vs_hdsp_256x32 ram0
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vs_hdsp_256x32_bw ram0
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`endif
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`endif
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(
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(
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.CK (clk),
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.CK (clk),
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.CEN (!ce),
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.CEN (!ce),
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.WEN (!we),
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.WEN (!we),
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| Line 148... |
Line 197... |
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`else // !ETH_VIRTUAL_SILICON_RAM
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`else // !ETH_VIRTUAL_SILICON_RAM
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`ifdef ETH_ARTISAN_RAM
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`ifdef ETH_ARTISAN_RAM
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`ifdef ETH_BIST
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`ifdef ETH_BIST
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art_hssp_256x32_bist ram0_bist
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//art_hssp_256x32_bist ram0_bist
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art_hssp_256x32_bw_bist ram0_bist
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`else
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`else
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art_hssp_256x32 ram0
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//art_hssp_256x32 ram0
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art_hssp_256x32_bw ram0
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`endif
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`endif
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(
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(
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.CLK (clk),
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.CLK (clk),
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.CEN (!ce),
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.CEN (!ce),
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.WEN (!we),
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.WEN (!we),
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| Line 178... |
Line 229... |
//
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//
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//
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//
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// Generic RAM's registers and wires
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// Generic RAM's registers and wires
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//
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//
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reg [31:0] mem [255:0]; // RAM content
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reg [ 7: 0] mem0 [255:0]; // RAM content
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reg [15: 8] mem1 [255:0]; // RAM content
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reg [23:16] mem2 [255:0]; // RAM content
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reg [31:24] mem3 [255:0]; // RAM content
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wire [31:0] q; // RAM output
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wire [31:0] q; // RAM output
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reg [7:0] raddr; // RAM read address
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reg [7:0] raddr; // RAM read address
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//
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//
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// Data output drivers
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// Data output drivers
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//
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//
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| Line 195... |
Line 249... |
// read operation
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// read operation
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always@(posedge clk)
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always@(posedge clk)
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if (ce) // && !we)
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if (ce) // && !we)
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raddr <= #1 addr; // read address needs to be registered to read clock
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raddr <= #1 addr; // read address needs to be registered to read clock
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assign #1 q = rst ? {32{1'b0}} : mem[raddr];
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assign #1 q = rst ? {32{1'b0}} : {mem3[raddr], mem2[raddr], mem1[raddr], mem0[raddr]};
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// write operation
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// write operation
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always@(posedge clk)
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always@(posedge clk)
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if (ce && we)
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begin
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mem[addr] <= #1 di;
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if (ce && we[3])
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mem3[addr] <= #1 di[31:24];
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if (ce && we[2])
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mem2[addr] <= #1 di[23:16];
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if (ce && we[1])
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mem1[addr] <= #1 di[15: 8];
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if (ce && we[0])
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mem0[addr] <= #1 di[ 7: 0];
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end
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// Task prints range of memory
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// Task prints range of memory
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// *** Remember that tasks are non reentrant, don't call this task in parallel for multiple instantiations.
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// *** Remember that tasks are non reentrant, don't call this task in parallel for multiple instantiations.
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task print_ram;
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task print_ram;
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input [7:0] start;
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input [7:0] start;
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input [7:0] finish;
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input [7:0] finish;
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integer rnum;
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integer rnum;
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begin
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begin
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for (rnum=start;rnum<=finish;rnum=rnum+1)
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for (rnum=start;rnum<=finish;rnum=rnum+1)
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$display("Addr %h = %h",rnum,mem[rnum]);
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$display("Addr %h = %0h %0h %0h %0h",rnum,mem3[rnum],mem2[rnum],mem1[rnum],mem0[rnum]);
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end
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end
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endtask
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endtask
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`endif // !ETH_ARTISAN_RAM
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`endif // !ETH_ARTISAN_RAM
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`endif // !ETH_VIRTUAL_SILICON_RAM
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`endif // !ETH_VIRTUAL_SILICON_RAM
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