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[/] [ethmac/] [branches/] [unneback/] [rtl/] [verilog/] [eth_top.v] - Diff between revs 301 and 302

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Rev 301 Rev 302
Line 39... Line 39...
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.47  2003/10/06 15:43:45  knguyen
 
// Update RxEnSync only when mrxdv_pad_i is inactive (LOW).
 
//
// Revision 1.46  2003/01/30 13:30:22  tadejm
// Revision 1.46  2003/01/30 13:30:22  tadejm
// Defer indication changed.
// Defer indication changed.
//
//
// Revision 1.45  2003/01/22 13:49:26  tadejm
// Revision 1.45  2003/01/22 13:49:26  tadejm
// When control packets were received, they were ignored in some cases.
// When control packets were received, they were ignored in some cases.
Line 248... Line 251...
 
 
  // Bist
  // Bist
`ifdef ETH_BIST
`ifdef ETH_BIST
  ,
  ,
  // debug chain signals
  // debug chain signals
  scanb_rst,      // bist scan reset
  mbist_si_i,       // bist scan serial in
  scanb_clk,      // bist scan clock
  mbist_so_o,       // bist scan serial out
  scanb_si,       // bist scan serial in
  mbist_ctrl_i        // bist chain shift control
  scanb_so,       // bist scan serial out
 
  scanb_en        // bist scan shift enable
 
`endif
`endif
 
 
);
);
 
 
 
 
Line 318... Line 319...
 
 
output          int_o;         // Interrupt output
output          int_o;         // Interrupt output
 
 
// Bist
// Bist
`ifdef ETH_BIST
`ifdef ETH_BIST
input   scanb_rst;      // bist scan reset
input   mbist_si_i;       // bist scan serial in
input   scanb_clk;      // bist scan clock
output  mbist_so_o;       // bist scan serial out
input   scanb_si;       // bist scan serial in
input [`ETH_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;       // bist chain shift control
output  scanb_so;       // bist scan serial out
 
input   scanb_en;       // bist scan shift enable
 
`endif
`endif
 
 
wire     [7:0]  r_ClkDiv;
wire     [7:0]  r_ClkDiv;
wire            r_MiiNoPre;
wire            r_MiiNoPre;
wire    [15:0]  r_CtrlData;
wire    [15:0]  r_CtrlData;
Line 888... Line 887...
  .CarrierSenseLost(CarrierSenseLost),.ReceivedPacketGood(ReceivedPacketGood),  .AddressMiss(AddressMiss),
  .CarrierSenseLost(CarrierSenseLost),.ReceivedPacketGood(ReceivedPacketGood),  .AddressMiss(AddressMiss),
  .ReceivedPauseFrm(ReceivedPauseFrm)
  .ReceivedPauseFrm(ReceivedPauseFrm)
 
 
`ifdef ETH_BIST
`ifdef ETH_BIST
  ,
  ,
  .scanb_rst      (scanb_rst),
  .mbist_si_i       (mbist_si_i),
  .scanb_clk      (scanb_clk),
  .mbist_so_o       (mbist_so_o),
  .scanb_si       (scanb_si),
  .mbist_ctrl_i       (mbist_ctrl_i)
  .scanb_so       (scanb_so),
 
  .scanb_en       (scanb_en)
 
`endif
`endif
);
);
 
 
 
 
 
 

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