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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.48 2003/10/17 07:46:16 markom
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// mbist signals updated according to newest convention
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//
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// Revision 1.47 2003/10/06 15:43:45 knguyen
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// Revision 1.47 2003/10/06 15:43:45 knguyen
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// Update RxEnSync only when mrxdv_pad_i is inactive (LOW).
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// Update RxEnSync only when mrxdv_pad_i is inactive (LOW).
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//
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//
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// Revision 1.46 2003/01/30 13:30:22 tadejm
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// Revision 1.46 2003/01/30 13:30:22 tadejm
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// Defer indication changed.
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// Defer indication changed.
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);
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);
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wire RegCs; // Connected to registers
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wire [3:0] RegCs; // Connected to registers
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wire [31:0] RegDataOut; // Multiplexed to wb_dat_o
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wire [31:0] RegDataOut; // Multiplexed to wb_dat_o
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wire r_RecSmall; // Receive small frames
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wire r_RecSmall; // Receive small frames
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wire r_LoopBck; // Loopback
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wire r_LoopBck; // Loopback
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wire r_TxEn; // Tx Enable
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wire r_TxEn; // Tx Enable
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wire r_RxEn; // Rx Enable
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wire r_RxEn; // Rx Enable
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wire TxE_IRQ; // Interrupt Tx Error
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wire TxE_IRQ; // Interrupt Tx Error
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wire RxB_IRQ; // Interrupt Rx Buffer
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wire RxB_IRQ; // Interrupt Rx Buffer
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wire RxE_IRQ; // Interrupt Rx Error
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wire RxE_IRQ; // Interrupt Rx Error
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wire Busy_IRQ; // Interrupt Busy (lack of buffers)
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wire Busy_IRQ; // Interrupt Busy (lack of buffers)
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wire DWord;
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//wire DWord;
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wire ByteSelected;
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wire [3:0] ByteSel;
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wire BDAck;
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wire BDAck;
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wire [31:0] BD_WB_DAT_O; // wb_dat_o that comes from the Wishbone module (for buffer descriptors read/write)
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wire [31:0] BD_WB_DAT_O; // wb_dat_o that comes from the Wishbone module (for buffer descriptors read/write)
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wire BDCs; // Buffer descriptor CS
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wire [3:0] BDCs; // Buffer descriptor CS
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wire CsMiss; // When access to the address between 0x800 and 0xfff occurs, acknowledge is set
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wire CsMiss; // When access to the address between 0x800 and 0xfff occurs, acknowledge is set
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// but data is not valid.
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// but data is not valid.
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wire temp_wb_ack_o;
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wire temp_wb_ack_o;
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wire [31:0] temp_wb_dat_o;
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wire [31:0] temp_wb_dat_o;
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reg temp_wb_ack_o_reg;
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reg temp_wb_ack_o_reg;
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reg [31:0] temp_wb_dat_o_reg;
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reg [31:0] temp_wb_dat_o_reg;
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reg temp_wb_err_o_reg;
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reg temp_wb_err_o_reg;
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`endif
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`endif
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assign DWord = &wb_sel_i;
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//assign DWord = &wb_sel_i;
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assign RegCs = wb_stb_i & wb_cyc_i & DWord & ~wb_adr_i[11] & ~wb_adr_i[10]; // 0x0 - 0x3FF
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assign ByteSelected = |wb_sel_i;
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assign BDCs = wb_stb_i & wb_cyc_i & DWord & ~wb_adr_i[11] & wb_adr_i[10]; // 0x400 - 0x7FF
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assign RegCs[3] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[3]; // 0x0 - 0x3FF
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assign CsMiss = wb_stb_i & wb_cyc_i & DWord & wb_adr_i[11]; // 0x800 - 0xfFF
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assign RegCs[2] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[2]; // 0x0 - 0x3FF
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assign temp_wb_ack_o = RegCs | BDAck;
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assign RegCs[1] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[1]; // 0x0 - 0x3FF
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assign temp_wb_dat_o = (RegCs & ~wb_we_i)? RegDataOut : BD_WB_DAT_O;
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assign RegCs[0] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[0]; // 0x0 - 0x3FF
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assign temp_wb_err_o = wb_stb_i & wb_cyc_i & (~DWord | CsMiss);
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assign BDCs[3] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & wb_adr_i[10] & wb_sel_i[3]; // 0x400 - 0x7FF
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assign BDCs[2] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & wb_adr_i[10] & wb_sel_i[2]; // 0x400 - 0x7FF
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assign BDCs[1] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & wb_adr_i[10] & wb_sel_i[1]; // 0x400 - 0x7FF
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assign BDCs[0] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & wb_adr_i[10] & wb_sel_i[0]; // 0x400 - 0x7FF
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assign CsMiss = wb_stb_i & wb_cyc_i & ByteSelected & wb_adr_i[11]; // 0x800 - 0xfFF
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assign temp_wb_ack_o = (|RegCs) | BDAck;
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assign temp_wb_dat_o = ((|RegCs) & ~wb_we_i)? RegDataOut : BD_WB_DAT_O;
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assign temp_wb_err_o = wb_stb_i & wb_cyc_i & (~ByteSelected | CsMiss);
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`ifdef ETH_REGISTERED_OUTPUTS
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`ifdef ETH_REGISTERED_OUTPUTS
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assign wb_ack_o = temp_wb_ack_o_reg;
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assign wb_ack_o = temp_wb_ack_o_reg;
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assign wb_dat_o[31:0] = temp_wb_dat_o_reg;
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assign wb_dat_o[31:0] = temp_wb_dat_o_reg;
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assign wb_err_o = temp_wb_err_o_reg;
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assign wb_err_o = temp_wb_err_o_reg;
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