| Line 39... |
Line 39... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.49 2003/11/12 18:24:59 tadejm
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// WISHBONE slave changed and tested from only 32-bit accesss to byte access.
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//
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// Revision 1.48 2003/10/17 07:46:16 markom
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// Revision 1.48 2003/10/17 07:46:16 markom
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// mbist signals updated according to newest convention
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// mbist signals updated according to newest convention
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//
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//
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// Revision 1.47 2003/10/06 15:43:45 knguyen
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// Revision 1.47 2003/10/06 15:43:45 knguyen
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// Update RxEnSync only when mrxdv_pad_i is inactive (LOW).
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// Update RxEnSync only when mrxdv_pad_i is inactive (LOW).
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| Line 414... |
Line 417... |
wire r_TxPauseRq; // Transmit PAUSE request
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wire r_TxPauseRq; // Transmit PAUSE request
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wire [3:0] r_MaxRet; //
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wire [3:0] r_MaxRet; //
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wire r_NoBckof; //
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wire r_NoBckof; //
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wire r_ExDfrEn; //
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wire r_ExDfrEn; //
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wire TX_BD_NUM_Wr; // Write enable that writes RX_BD_NUM to the registers.
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wire r_TxFlow; // Tx flow control enable
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wire r_TxFlow; // Tx flow control enable
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wire r_IFG; // Minimum interframe gap for incoming packets
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wire r_IFG; // Minimum interframe gap for incoming packets
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wire TxB_IRQ; // Interrupt Tx Buffer
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wire TxB_IRQ; // Interrupt Tx Buffer
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wire TxE_IRQ; // Interrupt Tx Error
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wire TxE_IRQ; // Interrupt Tx Error
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| Line 512... |
Line 514... |
.r_WCtrlData(r_WCtrlData), .r_RStat(r_RStat), .r_ScanStat(r_ScanStat),
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.r_WCtrlData(r_WCtrlData), .r_RStat(r_RStat), .r_ScanStat(r_ScanStat),
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.r_RGAD(r_RGAD), .r_FIAD(r_FIAD), .r_CtrlData(r_CtrlData),
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.r_RGAD(r_RGAD), .r_FIAD(r_FIAD), .r_CtrlData(r_CtrlData),
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.NValid_stat(NValid_stat), .Busy_stat(Busy_stat),
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.NValid_stat(NValid_stat), .Busy_stat(Busy_stat),
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.LinkFail(LinkFail), .r_MAC(r_MAC), .WCtrlDataStart(WCtrlDataStart),
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.LinkFail(LinkFail), .r_MAC(r_MAC), .WCtrlDataStart(WCtrlDataStart),
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.RStatStart(RStatStart), .UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg), .Prsd(Prsd),
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.RStatStart(RStatStart), .UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg), .Prsd(Prsd),
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.r_TxBDNum(r_TxBDNum), .TX_BD_NUM_Wr(TX_BD_NUM_Wr), .int_o(int_o),
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.r_TxBDNum(r_TxBDNum), .int_o(int_o),
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.r_HASH0(r_HASH0), .r_HASH1(r_HASH1), .r_TxPauseRq(r_TxPauseRq),
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.r_HASH0(r_HASH0), .r_HASH1(r_HASH1), .r_TxPauseRq(r_TxPauseRq),
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.r_TxPauseTV(r_TxPauseTV), .RstTxPauseRq(RstTxPauseRq), .TxCtrlEndFrm(TxCtrlEndFrm),
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.r_TxPauseTV(r_TxPauseTV), .RstTxPauseRq(RstTxPauseRq), .TxCtrlEndFrm(TxCtrlEndFrm),
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.StartTxDone(StartTxDone), .TxClk(mtx_clk_pad_i), .RxClk(mrx_clk_pad_i),
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.StartTxDone(StartTxDone), .TxClk(mtx_clk_pad_i), .RxClk(mrx_clk_pad_i),
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.SetPauseTimer(SetPauseTimer)
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.SetPauseTimer(SetPauseTimer)
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| Line 880... |
Line 882... |
.TxDone(TxDone),
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.TxDone(TxDone),
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.PerPacketCrcEn(PerPacketCrcEn), .PerPacketPad(PerPacketPad),
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.PerPacketCrcEn(PerPacketCrcEn), .PerPacketPad(PerPacketPad),
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// Register
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// Register
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.r_TxEn(r_TxEn), .r_RxEn(r_RxEn), .r_TxBDNum(r_TxBDNum),
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.r_TxEn(r_TxEn), .r_RxEn(r_RxEn), .r_TxBDNum(r_TxBDNum),
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.TX_BD_NUM_Wr(TX_BD_NUM_Wr), .r_RxFlow(r_RxFlow), .r_PassAll(r_PassAll),
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.r_RxFlow(r_RxFlow), .r_PassAll(r_PassAll),
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//RX
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//RX
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.MRxClk(mrx_clk_pad_i), .RxData(RxData), .RxValid(RxValid),
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.MRxClk(mrx_clk_pad_i), .RxData(RxData), .RxValid(RxValid),
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.RxStartFrm(RxStartFrm), .RxEndFrm(RxEndFrm),
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.RxStartFrm(RxStartFrm), .RxEndFrm(RxEndFrm),
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.Busy_IRQ(Busy_IRQ), .RxE_IRQ(RxE_IRQ), .RxB_IRQ(RxB_IRQ),
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.Busy_IRQ(Busy_IRQ), .RxE_IRQ(RxE_IRQ), .RxB_IRQ(RxB_IRQ),
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