| Line 39... |
Line 39... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.50 2004/04/26 15:26:23 igorm
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// - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the
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// previous update of the core.
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// - TxBDAddress is set to 0 after the TX is enabled in the MODER register.
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// - RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER
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// register. (thanks to Mathias and Torbjorn)
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// - Multicast reception was fixed. Thanks to Ulrich Gries
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//
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// Revision 1.49 2003/11/12 18:24:59 tadejm
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// Revision 1.49 2003/11/12 18:24:59 tadejm
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// WISHBONE slave changed and tested from only 32-bit accesss to byte access.
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// WISHBONE slave changed and tested from only 32-bit accesss to byte access.
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//
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//
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// Revision 1.48 2003/10/17 07:46:16 markom
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// Revision 1.48 2003/10/17 07:46:16 markom
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// mbist signals updated according to newest convention
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// mbist signals updated according to newest convention
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| Line 294... |
Line 302... |
output m_wb_cyc_o;
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output m_wb_cyc_o;
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output m_wb_stb_o;
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output m_wb_stb_o;
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input m_wb_ack_i;
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input m_wb_ack_i;
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input m_wb_err_i;
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input m_wb_err_i;
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wire [29:0] m_wb_adr_tmp;
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`ifdef ETH_WISHBONE_B3
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`ifdef ETH_WISHBONE_B3
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output [2:0] m_wb_cti_o; // Cycle Type Identifier
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output [2:0] m_wb_cti_o; // Cycle Type Identifier
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output [1:0] m_wb_bte_o; // Burst Type Extension
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output [1:0] m_wb_bte_o; // Burst Type Extension
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`endif
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`endif
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| Line 434... |
Line 444... |
wire BDAck;
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wire BDAck;
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wire [31:0] BD_WB_DAT_O; // wb_dat_o that comes from the Wishbone module (for buffer descriptors read/write)
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wire [31:0] BD_WB_DAT_O; // wb_dat_o that comes from the Wishbone module (for buffer descriptors read/write)
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wire [3:0] BDCs; // Buffer descriptor CS
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wire [3:0] BDCs; // Buffer descriptor CS
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wire CsMiss; // When access to the address between 0x800 and 0xfff occurs, acknowledge is set
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wire CsMiss; // When access to the address between 0x800 and 0xfff occurs, acknowledge is set
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// but data is not valid.
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// but data is not valid.
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wire r_Pad;
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wire r_CrcEn;
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wire r_FullD;
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wire r_Pro;
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wire r_Bro;
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wire r_NoPre;
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wire r_RxFlow;
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wire r_PassAll;
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wire TxCtrlEndFrm;
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wire StartTxDone;
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wire SetPauseTimer;
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wire TxUsedDataIn;
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wire TxDoneIn;
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wire TxAbortIn;
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wire PerPacketPad;
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wire PadOut;
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wire PerPacketCrcEn;
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wire CrcEnOut;
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wire TxStartFrmOut;
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wire TxEndFrmOut;
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wire ReceivedPauseFrm;
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wire ControlFrmAddressOK;
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wire RxStatusWriteLatched_sync2;
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wire LateCollision;
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wire DeferIndication;
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wire LateCollLatched;
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wire DeferLatched;
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wire RstDeferLatched;
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wire CarrierSenseLost;
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wire temp_wb_ack_o;
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wire temp_wb_ack_o;
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wire [31:0] temp_wb_dat_o;
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wire [31:0] temp_wb_dat_o;
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wire temp_wb_err_o;
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wire temp_wb_err_o;
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| Line 456... |
Line 495... |
assign BDCs[3] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & wb_adr_i[10] & wb_sel_i[3]; // 0x400 - 0x7FF
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assign BDCs[3] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & wb_adr_i[10] & wb_sel_i[3]; // 0x400 - 0x7FF
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assign BDCs[2] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & wb_adr_i[10] & wb_sel_i[2]; // 0x400 - 0x7FF
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assign BDCs[2] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & wb_adr_i[10] & wb_sel_i[2]; // 0x400 - 0x7FF
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assign BDCs[1] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & wb_adr_i[10] & wb_sel_i[1]; // 0x400 - 0x7FF
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assign BDCs[1] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & wb_adr_i[10] & wb_sel_i[1]; // 0x400 - 0x7FF
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assign BDCs[0] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & wb_adr_i[10] & wb_sel_i[0]; // 0x400 - 0x7FF
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assign BDCs[0] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & wb_adr_i[10] & wb_sel_i[0]; // 0x400 - 0x7FF
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assign CsMiss = wb_stb_i & wb_cyc_i & ByteSelected & wb_adr_i[11]; // 0x800 - 0xfFF
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assign CsMiss = wb_stb_i & wb_cyc_i & ByteSelected & wb_adr_i[11]; // 0x800 - 0xfFF
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assign temp_wb_ack_o = (|RegCs) | BDAck;
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assign temp_wb_dat_o = ((|RegCs) & ~wb_we_i)? RegDataOut : BD_WB_DAT_O;
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assign temp_wb_dat_o = ((|RegCs) & ~wb_we_i)? RegDataOut : BD_WB_DAT_O;
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assign temp_wb_err_o = wb_stb_i & wb_cyc_i & (~ByteSelected | CsMiss);
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assign temp_wb_err_o = wb_stb_i & wb_cyc_i & (~ByteSelected | CsMiss);
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`ifdef ETH_REGISTERED_OUTPUTS
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`ifdef ETH_REGISTERED_OUTPUTS
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assign wb_ack_o = temp_wb_ack_o_reg;
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assign wb_ack_o = temp_wb_ack_o_reg;
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| Line 470... |
Line 508... |
assign wb_ack_o = temp_wb_ack_o;
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assign wb_ack_o = temp_wb_ack_o;
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assign wb_dat_o[31:0] = temp_wb_dat_o;
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assign wb_dat_o[31:0] = temp_wb_dat_o;
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assign wb_err_o = temp_wb_err_o;
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assign wb_err_o = temp_wb_err_o;
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`endif
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`endif
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`ifdef ETH_AVALON_BUS
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// As Avalon has no corresponding "error" signal, I (erroneously) will
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// send an ack to Avalon, even when accessing undefined memory. This
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// is a grey area in Avalon vs. Wishbone specs: My understanding
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// is that Avalon expects all memory addressable by the addr bus feeding
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// a slave to be, at the very minimum, readable.
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assign temp_wb_ack_o = (|RegCs) | BDAck | CsMiss;
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`else // WISHBONE
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assign temp_wb_ack_o = (|RegCs) | BDAck;
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`endif
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`ifdef ETH_REGISTERED_OUTPUTS
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`ifdef ETH_REGISTERED_OUTPUTS
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always @ (posedge wb_clk_i or posedge wb_rst_i)
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always @ (posedge wb_clk_i or posedge wb_rst_i)
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begin
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begin
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if(wb_rst_i)
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if(wb_rst_i)
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| Line 864... |
Line 911... |
.BDCs(BDCs), .WB_ACK_O(BDAck),
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.BDCs(BDCs), .WB_ACK_O(BDAck),
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.Reset(wb_rst_i),
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.Reset(wb_rst_i),
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// WISHBONE master
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// WISHBONE master
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.m_wb_adr_o(m_wb_adr_o), .m_wb_sel_o(m_wb_sel_o), .m_wb_we_o(m_wb_we_o),
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.m_wb_adr_o(m_wb_adr_tmp), .m_wb_sel_o(m_wb_sel_o), .m_wb_we_o(m_wb_we_o),
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.m_wb_dat_i(m_wb_dat_i), .m_wb_dat_o(m_wb_dat_o), .m_wb_cyc_o(m_wb_cyc_o),
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.m_wb_dat_i(m_wb_dat_i), .m_wb_dat_o(m_wb_dat_o), .m_wb_cyc_o(m_wb_cyc_o),
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.m_wb_stb_o(m_wb_stb_o), .m_wb_ack_i(m_wb_ack_i), .m_wb_err_i(m_wb_err_i),
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.m_wb_stb_o(m_wb_stb_o), .m_wb_ack_i(m_wb_ack_i), .m_wb_err_i(m_wb_err_i),
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`ifdef ETH_WISHBONE_B3
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`ifdef ETH_WISHBONE_B3
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.m_wb_cti_o(m_wb_cti_o), .m_wb_bte_o(m_wb_bte_o),
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.m_wb_cti_o(m_wb_cti_o), .m_wb_bte_o(m_wb_bte_o),
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| Line 896... |
Line 943... |
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.InvalidSymbol(InvalidSymbol), .LatchedCrcError(LatchedCrcError), .RxLength(RxByteCnt),
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.InvalidSymbol(InvalidSymbol), .LatchedCrcError(LatchedCrcError), .RxLength(RxByteCnt),
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.RxLateCollision(RxLateCollision), .ShortFrame(ShortFrame), .DribbleNibble(DribbleNibble),
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.RxLateCollision(RxLateCollision), .ShortFrame(ShortFrame), .DribbleNibble(DribbleNibble),
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.ReceivedPacketTooBig(ReceivedPacketTooBig), .LoadRxStatus(LoadRxStatus), .RetryCntLatched(RetryCntLatched),
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.ReceivedPacketTooBig(ReceivedPacketTooBig), .LoadRxStatus(LoadRxStatus), .RetryCntLatched(RetryCntLatched),
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.RetryLimit(RetryLimit), .LateCollLatched(LateCollLatched), .DeferLatched(DeferLatched),
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.RetryLimit(RetryLimit), .LateCollLatched(LateCollLatched), .DeferLatched(DeferLatched),
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.RstDeferLatched(RstDeferLatched),
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.CarrierSenseLost(CarrierSenseLost),.ReceivedPacketGood(ReceivedPacketGood), .AddressMiss(AddressMiss),
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.CarrierSenseLost(CarrierSenseLost),.ReceivedPacketGood(ReceivedPacketGood), .AddressMiss(AddressMiss),
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.ReceivedPauseFrm(ReceivedPauseFrm)
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.ReceivedPauseFrm(ReceivedPauseFrm)
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`ifdef ETH_BIST
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`ifdef ETH_BIST
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,
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,
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| Line 907... |
Line 955... |
.mbist_so_o (mbist_so_o),
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.mbist_so_o (mbist_so_o),
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.mbist_ctrl_i (mbist_ctrl_i)
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.mbist_ctrl_i (mbist_ctrl_i)
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`endif
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`endif
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);
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);
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assign m_wb_adr_o = {m_wb_adr_tmp, 2'h0};
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// Connecting MacStatus module
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// Connecting MacStatus module
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eth_macstatus macstatus1
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eth_macstatus macstatus1
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(
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(
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.MRxClk(mrx_clk_pad_i), .Reset(wb_rst_i),
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.MRxClk(mrx_clk_pad_i), .Reset(wb_rst_i),
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| Line 927... |
Line 975... |
.DribbleNibble(DribbleNibble), .ReceivedPacketTooBig(ReceivedPacketTooBig), .r_HugEn(r_HugEn),
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.DribbleNibble(DribbleNibble), .ReceivedPacketTooBig(ReceivedPacketTooBig), .r_HugEn(r_HugEn),
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.LoadRxStatus(LoadRxStatus), .RetryCnt(RetryCnt), .StartTxDone(StartTxDone),
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.LoadRxStatus(LoadRxStatus), .RetryCnt(RetryCnt), .StartTxDone(StartTxDone),
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.StartTxAbort(StartTxAbort), .RetryCntLatched(RetryCntLatched), .MTxClk(mtx_clk_pad_i),
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.StartTxAbort(StartTxAbort), .RetryCntLatched(RetryCntLatched), .MTxClk(mtx_clk_pad_i),
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.MaxCollisionOccured(MaxCollisionOccured), .RetryLimit(RetryLimit), .LateCollision(LateCollision),
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.MaxCollisionOccured(MaxCollisionOccured), .RetryLimit(RetryLimit), .LateCollision(LateCollision),
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.LateCollLatched(LateCollLatched), .DeferIndication(DeferIndication), .DeferLatched(DeferLatched),
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.LateCollLatched(LateCollLatched), .DeferIndication(DeferIndication), .DeferLatched(DeferLatched),
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.RstDeferLatched(RstDeferLatched),
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.TxStartFrm(TxStartFrmOut), .StatePreamble(StatePreamble), .StateData(StateData),
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.TxStartFrm(TxStartFrmOut), .StatePreamble(StatePreamble), .StateData(StateData),
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.CarrierSense(CarrierSense_Tx2), .CarrierSenseLost(CarrierSenseLost), .TxUsedData(TxUsedDataIn),
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.CarrierSense(CarrierSense_Tx2), .CarrierSenseLost(CarrierSenseLost), .TxUsedData(TxUsedDataIn),
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.LatchedMRxErr(LatchedMRxErr), .Loopback(r_LoopBck), .r_FullD(r_FullD)
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.LatchedMRxErr(LatchedMRxErr), .Loopback(r_LoopBck), .r_FullD(r_FullD)
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);
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);
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